Nanosheet Gate Structure for Backside Contact Placeholder Margin
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Solution Overview
Problem
Conventional nanosheet transistor processes face challenges in controlling the levels of backside source/drain contact placeholder structures without a bottom dielectric isolation layer, leading to risks of damaging the source/drain region and high on-resistance.
Innovation Solution
A semiconductor structure with a gate structure having varying gate thicknesses and inner spacers, including a bottom inner spacer structure with a greater vertical height than upper inner spacers, to provide a wider process window for backside source/drain contact placeholder formation, mitigating the risk of damage and high on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional nanosheet transistor processes are used without a bottom dielectric isolation layer, then device complexity is reduced, but manufacturing precision deteriorates leading to risks of damaging source/drain regions and high on-resistance
Solution Approach 1:
The gate structure is designed with non-uniform thickness, where the first gate thickness under the bottommost nanosheet is greater than the second gate thickness between nanosheets. This local variation in gate thickness provides enhanced placeholder position margin specifically at the critical bottom interface, improving manufacturing precision without requiring a bottom dielectric isolation layer throughout the entire structure.
2Manufacturing precision
If gate thickness is increased under the bottommost nanosheet, then placeholder position margin is improved, but device dimensions become more complex
Solution Approach 1:
The gate structure utilizes parameter changes by varying the gate thickness in different regions. The first gate thickness under the bottommost nanosheet is deliberately made greater than the second gate thickness between nanosheets. This parameter variation provides improved placeholder position margin while maintaining a relatively simple overall gate structure that can be fabricated using standard semiconductor manufacturing processes.
Data Source
AI summary
A semiconductor structure having improved placeholder position margin is provided. In embodiments, the semiconductor structure includes a nanosheet transistor including a plurality of spaced apart and vertically stacked semiconductor channel material nanosheets, a gate structure wrapped around each of the semiconductor channel material nanosheets, a first source/drain region located on a first side of the gate structure and a second source/drain region located on a second side of the gate structure. The gate structure has a first gate thickness under a bottommost semiconductor channel material nanosheet of the plurality of semiconductor channel material nanosheets that is greater than a second gate thickness that is located between the bottommost semiconductor channel material nanosheet and a nearest overlying semiconductor channel material nanosheet of the plurality of semiconductor channel material nanosheets.