Nanosheet Gate Structure With Recessed Vertical Spacer Capacitance Control
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Solution Overview
Problem
As integrated circuit devices scale down, there is an increased risk of process defects and reduced performance and reliability in nanosheet field-effect transistors, necessitating a new structure to enhance stability and accuracy.
Innovation Solution
The integrated circuit device incorporates a fin-type active region with a nanosheet stack surrounded by a gate line and a vertical structure featuring recessed portions on its side walls, which includes air spaces to reduce parasitic capacitance and increase effective channel width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If integrated circuit devices are scaled down to increase integration, then device density increases, but process defects increase and reliability decreases
Solution Approach 1:
The gate structure is segmented into multiple gate lines (first gate line and second gate line) that can be independently controlled, allowing separate optimization of drive strength and leakage control for different transistor regions, thereby improving reliability while maintaining high integration
Solution Approach 2:
The patent transitions from planar gate structures to three-dimensional vertical structures including nanosheet channels and stacked gate configurations, utilizing the vertical dimension to increase effective channel width and improve device performance without increasing footprint area
2Ease of manufacture
If conventional nanosheet transistor structures are used, then manufacturing is simpler, but performance and reliability are insufficient
Solution Approach 1:
The vertical structure serves multiple functions simultaneously: it acts as a spacer for gate alignment, provides mechanical support for the nanosheet stack, defines the channel region boundaries, and enables independent gate control, thereby improving reliability without significantly complicating the manufacturing process
Solution Approach 2:
The vertical structure is formed beforehand to establish precise geometric references and spacing relationships before subsequent gate and nanosheet fabrication steps, ensuring consistent alignment and reducing manufacturing variability that could affect reliability
Data Source
AI summary
An integrated circuit device includes a fin-type active region extending in a first horizontal direction on a substrate, a nanosheet stack including a plurality of nanosheets on the fin-type active region, a gate line extending around each of the plurality of nanosheets on the fin-type active region and extending in a second horizontal direction intersecting with the first horizontal direction, and a vertical structure at least partially overlapping the gate line in the second horizontal direction and including a side wall in contact with each of the plurality of nanosheets. The vertical structure further includes a recessed portion on the side wall thereof.