Nanosheet Transistor Gate Spacer Segmentation for Sub-10nm Pitches
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Solution Overview
Problem
Current methods for forming inner spacers in nanosheet transistors with small gate pitches face challenges due to the limited space between adjacent devices, which affects the structural integrity and electrical isolation of nanosheet channel regions.
Innovation Solution
The use of two-segment outer spacers and inner spacers, where the lower segment of the outer spacers is the same material as the inner spacers, with a self-aligned spacer etch to remove excess spacer material, ensuring selectivity and reducing the likelihood of gate pinch-off, facilitates the formation of these spacers in nanosheet transistors with gate pitches below 10 nm.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional single-segment spacers are used in nanosheet transistors with small gate pitches, then the fabrication process is simpler, but the structural integrity and electrical isolation between adjacent devices deteriorate
Solution Approach 1:
The spacer structure is divided into two distinct segments: an inner spacer formed directly on the gate electrode, and an outer spacer formed on the sidewalls of the inner spacer. This segmentation allows each spacer to perform its specific function optimally - the inner spacer provides electrical isolation close to the gate, while the outer spacer provides structural support and further isolation in the trench region, thereby resolving the contradiction between fabrication simplicity and electrical isolation reliability.
Solution Approach 2:
The inner spacer acts as an intermediary element between the gate electrode and the outer spacer. It is formed first and provides a foundation for the outer spacer, while also serving as the primary electrical isolation barrier. This intermediary structure enables the outer spacer to be positioned further from the gate, providing mechanical support without compromising the electrical isolation function.
2Productivity
If the space between gates is reduced below 10 nm to increase device density, then the device density improves, but the structural integrity of spacers and electrical isolation deteriorate
Solution Approach 1:
By segmenting the spacer into inner and outer portions, the patent enables effective spacer formation even when gate spacing is reduced below 10 nm. The inner spacer maintains a minimum thickness for electrical isolation, while the outer spacer provides additional structural support in the trench region, allowing the overall device density to increase without compromising spacer integrity.
Solution Approach 2:
The patent applies different materials and thicknesses to different segments of the spacer structure. The inner spacer uses a first material with specific properties optimized for electrical isolation, while the outer spacer uses a second material optimized for mechanical support. This local differentiation of properties allows the spacer system to maintain structural integrity at reduced gate pitches while enabling higher device density.
Data Source
AI summary
Embodiments of the invention are directed to method of fabricating a semiconductor device. A non-limiting embodiment of the method includes performing fabrication operations to form a nanosheet field effect transistor (FET) device on a substrate, wherein the fabrication operations include forming gate spacers along a gate region of the nanosheet FET device, wherein each of the gate spacers comprises an upper segment and a lower segment.