Nanosheet Gate Stack Engineering for Short-Channel Control
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in achieving further improvements in nanosheet FETs to address scaling down while maintaining device performance and reducing short-channel effects.
Innovation Solution
The fabrication process involves forming a stack of semiconductor layers with alternating materials of different etch selectivity and oxidation rates, followed by precise etching and deposition of dielectric and gate structures to create nanosheet channels surrounded by a gate electrode, enhancing gate control and mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor dimensions are scaled down to increase device density, then production efficiency and cost are improved, but short-channel effects increase and gate control deteriorates
Solution Approach 1:
The patent transitions from planar gate structures to three-dimensional gate-all-around (GAA) nanosheet structures. The gate electrode completely surrounds the channel in three dimensions, providing full depletion and superior gate control compared to traditional planar configurations. This dimensional change allows effective control of short-channel effects even at scaled dimensions.
Solution Approach 2:
The patent employs composite material structures including alternating layers of semiconductor materials (e.g., Si/SiGe) forming nanosheets, combined with high-k dielectric materials and metal gate electrodes. These composite structures enable optimized electrical properties, improved carrier mobility, and enhanced gate control while maintaining scalability.
2Reliability
If nanosheet FET structures are formed with gate-all-around configuration, then gate control and short-channel effect reduction are improved, but fabrication complexity increases
Solution Approach 1:
The patent divides the channel into multiple thin nanosheet layers separated by dielectric materials, with each nanosheet providing a controlled conduction path. This segmentation allows the gate to control each sheet independently while maintaining manufacturability through standardized processing steps for layer formation and patterning.
Solution Approach 2:
The gate-all-around structure serves multiple functions simultaneously: it provides electrical control of the channel, acts as a barrier to short-channel effects, enables stress engineering for mobility enhancement, and provides a platform for multi-sheet stacking to increase drive current. This multi-functionality justifies the enhanced fabrication complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves gate control and mobility in nanosheet FETs, reducing short-channel effects and enabling higher device density and performance.
Implementation Method 1
forming a stack of semiconductor layers with alternating materials of different etch selectivity
Implementation Method 2
alternating materials of different etch selectivity and oxidation rates
Data Source
AI summary
A method for forming a semiconductor device structure is provided. The method includes providing an interfacial layer around a semiconductor layer over a substrate, depositing a first high-k (HK) dielectric layer on the interfacial layer, depositing a first additive layer on the first HK dielectric layer, the first additive layer being formed of a zinc-containing material, depositing a second additive layer over the first additive layer, the second additive layer being formed of a lanthanum-containing material, forming a first capping layer over the second additive layer, subjecting the substrate to a first thermal treatment, depositing a second HK dielectric layer over the first HK dielectric layer, and providing a work function metal around the semiconductor layer.