Nanosheet Gate Stack Segmentation for Scalable Semiconductor Fabrication
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in improving processing and manufacturing efficiency as the complexity of semiconductor integrated circuits (ICs) increases with scaling down, requiring innovative methods to enhance production efficiency and reduce costs while maintaining device performance.
Innovation Solution
The method involves forming a semiconductor device structure with a stack of semiconductor layers, including nanosheet channels surrounded by gate electrodes, using epitaxial growth and advanced patterning techniques such as double-patterning or multi-patterning processes, and employing specific materials like SiGe and silicon oxide layers to optimize channel thickness and spacing for improved device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If geometry size is decreased to increase functional density, then production efficiency and cost are improved, but processing complexity increases
Solution Approach 1:
The patent divides the gate electrode into multiple segments (first gate electrode, second gate electrode, third gate electrode) separated by dielectric features. This segmentation allows for independent formation and control of each gate segment, simplifying the overall processing while achieving high functional density through multi-patterning techniques.
Solution Approach 2:
The patent transitions from planar 2D transistors to three-dimensional structures with vertical channel stacks and multi-layer gate electrodes. This dimensional change increases functional density without proportionally increasing processing complexity by utilizing vertical space efficiently.
2Quantity of substance
If functional density is increased through scaling down, then more devices fit per chip area, but manufacturing complexity increases
Solution Approach 1:
The patent forms dielectric features and spacer structures before final gate electrode formation. These preliminary structures serve as templates and guides for subsequent self-aligned patterning steps, enabling high functional density while reducing alignment complexity during manufacturing.
Solution Approach 2:
The patent introduces spacer structures and dielectric materials as intermediary elements that facilitate the formation of multiple gate electrodes. These intermediaries enable self-aligned patterning processes, reducing the need for complex multi-step lithography alignment while increasing device density.
3Reliability
If channel thickness is optimized for device performance, then transistor efficiency improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs self-aligned patterning where previously formed structures (spacers, dielectric features) automatically define the positions and dimensions of subsequent gate electrodes. This self-service mechanism inherently controls channel thickness and gate alignment without requiring additional high-precision lithography steps.
Solution Approach 2:
The patent utilizes epitaxial growth to precisely control semiconductor layer thickness and composition. By adjusting growth parameters during epitaxy, the channel thickness is controlled at the atomic layer level, achieving high device performance while maintaining manufacturing feasibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of more complex and efficient semiconductor devices with enhanced production efficiency, reducing manufacturing costs and improving device performance by optimizing channel dimensions and material selection.
Implementation Method 1
forming a semiconductor device structure with a stack of semiconductor layers, including nanosheet channels surrounded by gate electrodes, using epitaxial growth
Data Source
AI summary
A semiconductor device structure, along with methods of forming such, are described. The structure includes a first, second, and third gate electrode layers, a first dielectric feature disposed between the first and second gate electrode layers, a second dielectric feature disposed between the second and third gate electrode layers, a first seed layer in contact with the first gate electrode layer, the first dielectric feature, and the second gate electrode layer, a first conductive layer disposed on the first seed layer, a second seed layer in contact with the third gate electrode layer, a second conductive layer disposed on the second seed layer, and a dielectric material disposed on the second dielectric feature, the first conductive layer, and the second conductive layer. The dielectric material is between the first seed layer and the second seed layer and between the first conductive layer and the second conductive layer.