Nanosheet Gate Stack Layout for Threshold Voltage Tuning
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Solution Overview
Problem
In nanosheet devices, the thick gate interfacial layer in the I/O area limits the space between channel semiconductor layers, preventing the formation of a work function metal layer and merging high-k dielectric layers, which hinders the achievement of the desired threshold voltage and degrades device performance.
Innovation Solution
The channel semiconductor layers in the I/O area are trimmed to be thinner than those in the core area, enlarging the space between them, allowing for the formation of a work function metal layer and enabling dipole processing of high-k dielectric layers, thereby facilitating the formation of metal gate structures and adjusting the threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick gate interfacial layer is used in the I/O area, then gate control is improved, but the space between channel semiconductor layers is reduced, preventing work function metal layer formation
Solution Approach 1:
The patent applies different interfacial layer thicknesses to different areas of the device. The I/O area has a thicker gate interfacial layer (first thickness) for improved gate control, while the core area has a thinner gate interfacial layer (second thickness, less than the first thickness) that allows sufficient space between channel semiconductor layers for work function metal layer formation. This local differentiation resolves the contradiction by optimizing each area for its specific function.
2Productivity
If the space between channel semiconductor layers is limited, then device scaling is achieved, but high-k dielectric layers merge and work function metal cannot be formed
Solution Approach 1:
The patent creates different structural configurations in different areas. In the core area, the thinner gate interfacial layer enables sufficient spacing between channel semiconductor layers to accommodate both high-k dielectric layers and work function metal layers without merging. In the I/O area, the thicker gate interfacial layer provides optimal gate control. This local differentiation allows device scaling to be achieved in the core area while maintaining manufacturability of work function metal layers.
3Ease of manufacture
If uniform channel semiconductor layer thickness is used across all areas, then fabrication simplicity is maintained, but I/O area performance is degraded due to insufficient space for gate electrode formation
Solution Approach 1:
The patent implements different channel semiconductor layer thicknesses in different areas. The I/O area has thinner channel semiconductor layers that create sufficient space between layers to accommodate the thicker gate interfacial layer and enable proper gate electrode formation with work function metal layers. The core area has thicker channel semiconductor layers that provide adequate channel depth for optimal transistor performance. This local differentiation resolves the contradiction by optimizing each area for its specific performance requirements.
Solution Approach 2:
The patent segments the device into distinct functional areas (I/O area and core area) with different structural parameters. This segmentation allows independent optimization of each area - the I/O area with its thinner channels and thicker interfacial layer for robust gate control, and the core area with thicker channels and thinner interfacial layer for high-performance transistor operation. The segmentation resolves the contradiction by allowing different fabrication parameters in different segments rather than requiring uniform parameters throughout.
Data Source
AI summary
Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises first semiconductor layers and second semiconductor layers over a substrate, wherein the first semiconductor layers and the second semiconductor layers are separated and stacked up, and a thickness of each second semiconductor layer is less than a thickness of each first semiconductor layer; a first interfacial layer around each first semiconductor layer; a second interfacial layer around each second semiconductor layer; a first dipole gate dielectric layer around each first semiconductor layer and over the first interfacial layer; a second dipole gate dielectric layer around each second semiconductor layer and over the second interfacial layer; a first gate electrode around each first semiconductor layer and over the first dipole gate dielectric layer; and a second gate electrode around each second semiconductor layer and over the second dipole gate dielectric layer.