Nanosheet Gate Stack Layout for Threshold Voltage Uniformity
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, challenges arise in maintaining uniformity of the work function material thickness, leading to variations in threshold voltage, which affects device performance.
Innovation Solution
A method is developed to form nanosheet field-effect transistors (NSFETs) by creating a multi-layer stack over a substrate, patterning it to form fins and nanostructures, and using a replacement gate process to form metal gate structures, ensuring uniform work function material thickness around nanosheets, preventing merging and thus reducing threshold voltage variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication methods are used to deposit work function material around nanosheets, then the manufacturing process is simple, but the work function material thickness becomes non-uniform causing threshold voltage variations
Solution Approach 1:
The gate structure is segmented into multiple functional layers: gate dielectric material layer, first liner material layer, work function material layer, and second liner material layer. Each layer is deposited separately with controlled thickness, allowing precise control over work function material thickness uniformity while preventing merging between adjacent nanosheets.
Solution Approach 2:
The gate dielectric material and liner material layers are deposited beforehand to create a protective framework around each nanosheet before depositing the work function material. This preliminary structure prevents direct contact and merging of work function material between adjacent nanosheets, ensuring uniform thickness distribution.
2Productivity
If feature size is reduced to increase integration density, then more components can be integrated into a given area, but threshold voltage variations increase due to non-uniform work function material thickness
Solution Approach 1:
By segmenting the gate structure into multiple controlled layers with liner materials separating adjacent nanosheets, the invention maintains precise control over work function material thickness even as feature sizes are reduced, thereby maintaining threshold voltage uniformity while achieving higher integration density.
Solution Approach 2:
The liner material layers act as intermediary barriers between adjacent nanosheets, preventing the merging of work function material while allowing each nanosheet to maintain its own uniform work function material layer, thus preserving electrical characteristics at smaller feature sizes.
3Ease of manufacture
If work function material is deposited without liner materials, then the fabrication process is simpler, but the work function material merges between adjacent nanosheets causing performance degradation
Solution Approach 1:
The gate structure is divided into discrete layers with liner materials separating the work function material around each nanosheet, preventing merging while maintaining a relatively straightforward fabrication process through sequential deposition of each layer.
Solution Approach 2:
Liner material layers serve as intermediary barriers that physically separate adjacent nanosheets during work function material deposition, preventing merging and ensuring consistent device performance without significantly complicating the fabrication process.
Data Source
AI summary
A semiconductor device includes a fin protruding above a substrate; source/drain regions over the fin; nanosheets between the source/drain regions; and a gate structure over the fin and between the source/drain regions. The gate structure includes: a gate dielectric material around each of the nanosheets; a first liner material around the gate dielectric material; a work function material around the first liner material; a second liner material around the work function material; and a gate electrode material around at least portions of the second liner material.