Nanosheet Gate Structure With Strained Source/Drain for Scaled ICs
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Solution Overview
Problem
As integrated circuit devices downscale, ensuring high operating speed and accuracy becomes crucial, but existing technologies face challenges in achieving both performance and reliability in fin-type active regions with nanosheet structures.
Innovation Solution
The integrated circuit device incorporates a fin-type active region with nanosheets, a gate line system including main and sub-gate portions, and source/drain regions with single crystalline semiconductor bodies and stacking fault surfaces, which apply strain to nanosheets, enhancing carrier mobility and transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If integrated circuit devices downscale to improve integration density, then productivity increases, but manufacturing precision and reliability deteriorate
Solution Approach 1:
The device structure is segmented into multiple functional layers: fin-type active region, nanosheet channel layer, inner insulating spacer, and source/drain regions with stacking fault surfaces. This segmentation allows each component to be optimized independently for its specific function while maintaining overall device performance during downscaling.
Solution Approach 2:
Different regions of the device are assigned different material compositions and structural properties. The source/drain regions contain stacking fault surfaces with specific orientations, the channel region uses nanosheets with controlled thickness, and the insulating spacer provides localized dielectric support. This local quality differentiation enables precise control of carrier mobility and device characteristics at scaled dimensions.
2Productivity
If device dimensions are reduced to increase integration, then productivity improves, but reliability deteriorates
Solution Approach 1:
The device employs composite material structures combining semiconductor materials (fin-type active region, nanosheets), insulating materials (inner insulating spacer), and source/drain materials with stacking fault surfaces. This composite approach allows optimization of electrical, mechanical, and thermal properties independently, maintaining reliability even as overall device dimensions are reduced for higher integration.
3Reliability
If complex gate structures are added to improve carrier mobility, then device performance improves, but device complexity increases
Solution Approach 1:
The gate structure extends into the vertical dimension with the sub-gate portion positioned between the fin-type active region and nanosheet, and the inner insulating spacer providing vertical separation. This three-dimensional gate configuration enhances carrier mobility through improved electrostatic control without requiring excessive planar complexity, as the gating effect is achieved through vertical stacking rather than lateral expansion.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the mobility of carriers in the channel region, leading to enhanced performance and reliability of the transistors, addressing the challenges of scaling while maintaining accuracy and speed.
Implementation Method 1
at least one lower stacking fault surface linearly extending from the inner insulating spacer through the single crystalline semiconductor body toward an inside of the source/drain region
Data Source
AI summary
An integrated circuit (IC) device includes a fin-type active region extending longitudinally in a first lateral direction on a substrate. A nanosheet is apart from a fin top surface of the fin-type active region in a vertical direction. An inner insulating spacer is between the substrate and the nanosheet. A gate line includes a main gate portion and a sub-gate portion. The main gate portion extends longitudinally in a second lateral direction on the nanosheet. The sub-gate portion is integrally connected to the main gate portion and between the substrate and the nanosheet. A source/drain region is in contact with the inner insulating spacer and the nanosheet. The source/drain region includes a single crystalline semiconductor body and at least one lower stacking fault surface linearly extending from the inner insulating spacer through the single crystalline semiconductor body.