Nanosheet IC Gate Formation With Reduced Dielectric Wall Height
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Solution Overview
Problem
Conventional nano-sheet-based devices face challenges in scaling down due to restricted material access for feature formation and removal, leading to threshold voltage issues and performance degradation, particularly in devices like push-rule Static Random-Access Memory cells.
Innovation Solution
The method involves forming dielectric walls with reduced height to minimize material flow restrictions, allowing easier access to channel layers and improved gate layer formation, thereby enhancing channel release and gate layer deposition processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If spacing between adjacent channel layers is continuously shrunk to improve gate control and reduce short-channel effects, then device performance is improved, but material access to those spaces becomes more restricted
Solution Approach 1:
The patent segments the gate structure into multiple discrete gate electrodes that can be independently formed and controlled. This segmentation allows material to access each gate electrode through separate pathways, overcoming the restriction caused by continuous scaling of channel layer spacing. Each gate electrode can be formed through its own deposition and patterning process, ensuring complete coverage even in tightly spaced configurations.
Solution Approach 2:
The patent introduces a vertical dimension to gate electrode formation by forming gates that extend through the thickness of the semiconductor layer. This dimensional approach allows material access from multiple directions (top and sidewalls) rather than relying solely on horizontal access, enabling effective gate formation even when channel layer spacing is continuously reduced.
2Adaptability or versatility
If conventional nano-sheet-based devices are used, then compatibility with CMOS processes is maintained, but threshold voltage issues arise due to restricted material access
Solution Approach 1:
The patent performs preliminary actions by forming sacrificial layers and mandrel structures before forming the gate electrodes. These preliminary structures guide the subsequent material deposition and patterning processes, ensuring that gate material is deposited uniformly and completely across all channel layers. This preliminary structuring prevents threshold voltage variations that would otherwise result from incomplete material access.
Solution Approach 2:
The patent uses sacrificial layers and mandrel structures as intermediary elements that facilitate precise gate formation. These intermediary structures temporarily occupy space during fabrication, then are removed to reveal the precisely formed gate electrodes. This intermediary approach enables accurate threshold voltage control by ensuring complete and uniform gate material deposition, while maintaining compatibility with existing CMOS process flows.
Data Source
AI summary
A device includes a first and a second stacks of channel layers each extending from a first height to a second height. A first dielectric feature on a first side of the first stack and between the first and the second stacks extends from a third height to a fourth height. A second dielectric feature on a second side of the first stack opposite to the first side extends from the third height to a fifth height. A gate electrode extends continuously across a top surface of the first and the second stacks and extends to a sixth height. The fifth height is above the sixth height, the sixth height is above the second height, the second height is above the fourth height, the fourth height is above the first height, and the first height is above the third height.