Nanosheet Gate Work Function Layout for Dense Multi-Vt NSFETs
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Solution Overview
Problem
The vertical spacing between nanosheet channel structures in nanosheet field effect transistors (NSFETs) limits the effectiveness of doping and dipole engineering for gate dielectric layers, reducing the number of gate electrode layers and increasing the device height, which compromises device density and reliability, especially in static random access memory (SRAM) cells.
Innovation Solution
A method is developed to form NSFETs with different gate electrode structures by using dummy masking structures to prevent over-etching, allowing for the formation of multiple gate electrode layers without increasing the device height, enabling the creation of NSFETs with varying threshold voltages on the same substrate without sacrificing device density or reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the vertical spacing between nanosheet channel structures is reduced to increase device density, then device density improves, but the effectiveness of doping and dipole engineering for gate dielectric layers deteriorates
Solution Approach 1:
The patent transitions from vertical stacking to lateral arrangement of nanosheet channel structures. By arranging nanosheets side-by-side in the lateral dimension rather than stacking them vertically, the invention maintains adequate vertical spacing for effective doping and dipole engineering while achieving high device density through increased lateral integration.
Solution Approach 2:
The invention divides the channel structure into multiple discrete nanosheet segments arranged laterally. Each nanosheet can be independently doped and engineered with gate dielectric layers, allowing precise control over doping effectiveness while maintaining high overall device density through the segmented lateral configuration.
2Reliability
If the number of gate electrode layers is increased to improve device control, then device control improves, but device height increases compromising device density
Solution Approach 1:
The patent redistributes multiple gate electrode layers from the vertical dimension to the lateral dimension. Instead of stacking gates vertically which increases device height, the invention arranges gate electrode structures laterally around each nanosheet channel, providing comprehensive gate control while maintaining a compact vertical profile for high device density.
3Manufacturing precision
If dummy masking structures are used to prevent over-etching, then manufacturing precision improves, but device complexity increases
Solution Approach 1:
The patent introduces dummy masking structures as intermediary elements during the etching process. These temporary masking features prevent over-etching into adjacent nanosheet regions, ensuring precise pattern formation. The dummy masks are removed after serving their protective function, adding a controlled step to the manufacturing process that enables high precision without permanent complexity.
Data Source
AI summary
In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a first channel structure configured to transport charge carriers within a first transistor device and a first gate electrode layer wrapping around the first channel structure. A second channel structure is configured to transport charge carriers within a second transistor device. A second gate electrode layer wraps around the second channel structure. The second gate electrode layer continuously extends from around the second channel structure to cover the first gate electrode layer. A third channel structure is configured to transport charge carriers within a third transistor device. A third gate electrode layer wraps around the third channel structure. The third gate electrode layer continuously extends from around the third channel structure to cover the second gate electrode layer.