Nanosheet Transistor Inner Spacer Cavities for Epitaxy Protection

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Solution Overview

Problem

Current methods for fabricating nanosheet transistors face challenges in forming ideal inner spacers, leading to loss of source/drain epitaxy and electrical shorts, due to non-ideal spacer profiles and HCl leakage during channel release.

Innovation Solution

The method involves forming sacrificial silicon nitride top spacers and inner spacers on a nanosheet stack, removing them to re-open inner spacer cavities, and expanding these cavities by recessing sacrificial SiGe in the channel region to ensure complete separation, followed by conformal deposition of low dielectric constant materials for final spacers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional methods are used to form inner spacers, then fabrication process is simpler, but spacer profile is non-ideal leading to loss of source/drain epitaxy and electrical shorts

Engineering Contradiction:

Improveinner spacer profileVSAvoidfabrication process complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The fabrication process is divided into multiple sequential steps: forming initial spacers, creating indentations in SiGe layers, depositing additional spacer material, and performing selective etching. Each step refines the spacer structure incrementally to achieve the ideal profile while maintaining process control

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Indentations are formed in the SiGe layers before final spacer deposition. This preliminary shaping of the underlying layer guides the conformal deposition process to automatically create spacers with the desired profile, preventing epitaxial loss and electrical shorts

Inventive Principle:

Principle #10Preliminary action

2Productivity

If HCl is used for channel release, then etching process is effective, but HCl leakage occurs causing electrical shorts

Engineering Contradiction:

Improvechannel release efficiencyVSAvoidelectrical isolation

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The inner spacers act as intermediary protective barriers between the HCl etchant and the source/drain regions. These spacers prevent HCl from reaching and damaging critical interfaces, thereby eliminating electrical shorts while maintaining effective channel release

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

Protective spacer structures are formed before the HCl channel release step. These pre-formed spacers cushion and protect vulnerable interfaces from HCl exposure, preventing electrical shorts before they can occur

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

3Reliability

If inner spacers are formed to protect epitaxy, then epitaxial loss is prevented, but spacer deposition complexity increases

Engineering Contradiction:

Improveepitaxial protectionVSAvoidspacer formation steps

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The spacer formation utilizes changes in material properties at different stages: SiGe layers are selectively removed via etching, while silicon nitride spacers remain stable. This parameter change approach allows automatic differentiation and protection of epitaxial regions without additional complex processing

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach ensures optimal source/drain channel control, protects epitaxy during channel release, and prevents electrical shorts, improving the fabrication of nanosheet transistors by forming stable and functional inner spacer cavities.

Implementation Method 1

etching the sacrificial top spacer and sacrificial inner spacer to form an inner spacer cavity between the source/drain region and the at least one silicon-germanium layer

Methodology Applied

Scientific EffectEtching:

Implementation Method 2

conformal deposition of low dielectric constant materials for final spacers

Methodology Applied

Scientific EffectConformal deposition: Deposition (physical)

Data Source

PatentUS12154971B2Forming nanosheet transistor using sacrificial spacer and inner spacers

Publication Date: 2024.11.26 ADEIA SEMICONDUCTOR SOLUTIONS LLC

AI summary

Fabricating a nanosheet transistor includes receiving a substrate structure having a set of nanosheet layers stacked upon a substrate, the set of nanosheet layers including at least one silicon (Si) layer, at least one silicon-germanium (SiGe) layer, a fin formed in the nanosheet layers, a gate region formed within the fin, and a trench region adjacent to the fin. A top sacrificial spacer is formed upon the fin and the trench region and etched to form a trench in the trench region. An indentation is formed within the SiGe layer in the trench region, and a sacrificial inner spacer is formed within the indentation. A source/drain (S/D) region is formed within the trench. The sacrificial top spacer and sacrificial inner spacer are etched to form an inner spacer cavity between the S/D region and the SiGe layer. An inner spacer is formed within the inner spacer cavity.