Nanosheet Transistor Inner Spacer Formation for S/D Separation
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Solution Overview
Problem
Current methods for fabricating nanosheet transistors face challenges in forming ideal inner spacers, leading to potential loss of source/drain epitaxy and resulting in high resistance or electrical shorts.
Innovation Solution
The method involves forming a sacrificial silicon nitride top spacer and inner spacers on a nanosheet stack, removing them to reopen inner spacer cavities, and expanding these cavities by recessing sacrificial SiGe in the channel region, ensuring complete separation of the channel and S/D epitaxy regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional methods are used to form inner spacers in nanosheet transistors, then the fabrication process is simpler, but the inner spacer profiles are non-ideal leading to potential loss of source/drain epitaxy
Solution Approach 1:
The fabrication process is divided into multiple stages with different spacer formation methods. The top spacer is formed using a first method, while inner spacers are formed using a second method, allowing each to be optimized independently for their specific functional requirements.
Solution Approach 2:
Different regions of the device receive different treatments: the top spacer region receives a conformal deposition followed by etch-back, while the inner spacer region receives direct deposition on the nanosheet stack. This local differentiation ensures optimal profiles for each spacer type.
2Reliability
If inner spacers are not properly formed, then the fabrication process is simpler, but source/drain epitaxy may be lost resulting in high resistance or electrical shorts
Solution Approach 1:
The top spacer is formed preliminarily before the inner spacers. This top spacer serves as a protective structure during subsequent processing steps, preventing damage to the nanosheet stack and ensuring that inner spacers are formed with proper spacing and protection.
Solution Approach 2:
The top spacer acts as an intermediary protective structure that shields the nanosheet stack during inner spacer formation. It provides a physical barrier that prevents direct contact between processing tools and the delicate nanosheet structure, reducing the risk of epitaxy loss.
3Manufacturing precision
If a single spacer formation method is used, then the process is simpler, but optimal S/D channel control and variability cannot be achieved
Solution Approach 1:
The spacer system is segmented into top spacers and inner spacers with different formation methods. Top spacers are formed by conformal deposition and etch-back, while inner spacers are formed by direct deposition, allowing independent optimization of each spacer type for precise S/D channel control.
Solution Approach 2:
Different spacer regions are formed with locally optimized characteristics. The top spacer provides lateral definition and protection, while the inner spacer provides vertical spacing and field control, with each formed using the method best suited to its specific geometric and functional requirements.
Data Source
AI summary
Fabricating a nanosheet transistor includes receiving a substrate structure having a set of nanosheet layers stacked upon a substrate, the set of nanosheet layers including at least one silicon (Si) layer, at least one silicon-germanium (SiGe) layer, a fin formed in the nanosheet layers, a gate region formed within the fin, and a trench region adjacent to the fin. A top sacrificial spacer is formed upon the fin and the trench region and etched to form a trench in the trench region. An indentation is formed within the SiGe layer in the trench region, and a sacrificial inner spacer is formed within the indentation. A source/drain (S/D) region is formed within the trench. The sacrificial top spacer and sacrificial inner spacer are etched to form an inner spacer cavity between the S/D region and the SiGe layer. An inner spacer is formed within the inner spacer cavity.