Nanosheet I/O Fin Sidewall Encapsulation for Thick Gate Oxide
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Solution Overview
Problem
In nanosheet-based FETs, there is insufficient space to grow a thick oxide gate dielectric for I/O devices without increasing the gate dielectric thickness at the logic device region, which can degrade device performance.
Innovation Solution
A semiconductor structure is designed with a nanosheet fin for I/O devices featuring an alternating sequence of semiconductor sacrificial layers and channel layers, accompanied by an epitaxially grown encapsulation layer along the sidewalls, allowing for the deposition of a thick oxide gate dielectric without compromising the logic device region's performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick oxide gate dielectric is grown for I/O devices, then the gate dielectric thickness at the logic device region increases, but device performance degrades
Solution Approach 1:
The gate dielectric formation process is segmented into two distinct regions: I/O devices receive a thick oxide gate dielectric for high reliability, while logic devices maintain a thin gate dielectric for optimal performance. This spatial segmentation resolves the contradiction by allowing each region to have its required thickness independently.
Solution Approach 2:
Different gate dielectric thicknesses are applied to different device regions based on their specific requirements. The I/O device region receives a thick oxide layer for enhanced reliability, while the logic device region maintains a thin layer for superior electrical characteristics. This local differentiation eliminates the trade-off between reliability and performance.
2Reliability
If there is not enough room to grow a thick oxide for I/O devices, then space constraints are violated, but the gate dielectric thickness at logic device region increases
Solution Approach 1:
The solution transitions from a two-dimensional planar structure to a three-dimensional nanosheet architecture with vertical stacking. By utilizing the vertical dimension and creating multiple nanosheet layers, the structure provides sufficient volume for thick oxide growth in I/O regions without increasing the lateral footprint or compromising logic device spacing.
Solution Approach 2:
Multiple nanosheet layers are nested vertically within the device structure, creating a compact three-dimensional arrangement. This nesting approach maximizes the use of vertical space, allowing thick oxide gate dielectrics to be formed in I/O regions while maintaining compact dimensions suitable for advanced technology nodes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of nanosheet-based I/O devices with improved gate stack quality without degrading the logic device performance, facilitating better electro-static control and device scaling.
Implementation Method 1
an epitaxially grown encapsulation layer disposed along sidewalls of the second nanosheet fin
Data Source
AI summary
A semiconductor structure includes a first nanosheet fin extending vertically from a first region of a substrate corresponding to a logic device and a second nanosheet fin extending vertically from a second region of the substrate corresponding to an input/output device. The first nanosheet fin includes first semiconductor channel layers vertically stacked over the first region of the substrate, while the second nanosheet fin includes an alternating sequence of semiconductor sacrificial layers and second semiconductor channel layers. The semiconductor structure further includes an epitaxially grown encapsulation layer disposed only along sidewalls of the second nanosheet fin.