Nanosheet MOSFET Isolation Structure for Blocking Bulk Leakage
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Solution Overview
Problem
Multi-gate MOSFETs, particularly nanosheet transistors, face challenges in reducing cell size due to wider channel members, which complicates the formation of effective isolation structures to block bulk leakage, especially in high packing density applications like memory devices.
Innovation Solution
A deep isolation structure is formed at the well junction between p-type and n-type wells, featuring a notch that undercuts active regions, and is combined with shallow trench isolation to effectively block bulk leakage paths, using dielectric fins and hybrid fins to reduce cell dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If wider sheet-like channel members are used in MBC transistors to improve gate control and drive current, then superior gate control and drive current are achieved, but device widths increase making them less attractive in high packing density applications
Solution Approach 1:
The patent transitions from two-dimensional planar channel structures to three-dimensional vertically-stacked nanosheet channel members. By stacking multiple thin channel sheets vertically, the effective channel width is increased for superior gate control and drive current, while the lateral device footprint remains compact, resolving the contradiction between drive current and packing density
Solution Approach 2:
Multiple nanosheet channel members are nested vertically within a compact lateral footprint, with each sheet contributing to the effective channel width. The gate structure wraps around these nested sheets, providing enhanced gate control without increasing the lateral device dimensions, thus maintaining high packing density
2Reliability
If isolation structures are formed to isolate different device regions in MBC transistors, then device isolation is achieved, but the formation process becomes more complex
Solution Approach 1:
The isolation structure is segmented into two distinct components: shallow trench isolation features formed at the device periphery and deep isolation features formed in notches extending into the substrate. This segmentation allows each isolation component to be optimized independently and formed using standard semiconductor processing techniques, reducing overall process complexity while achieving superior isolation
3Object-generated harmful factors
If deep isolation structures with notches are formed to block bulk leakage paths, then bulk leakage is effectively blocked, but the manufacturing process becomes more complex
Solution Approach 1:
The deep isolation notches are formed preliminarily before the nanosheet channel members are released and positioned. This preliminary formation of isolation structures simplifies subsequent processing steps, as the notches are already in place to guide and constrain the channel member placement, making the overall manufacturing process more straightforward despite the added isolation functionality
Data Source
AI summary
Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary semiconductor structure according to the present disclosure includes a substrate having a p-type well or an n-type well, a first base portion over the p-type well, a second base portion over the n-type well, a first plurality of channel members over the first base portion, a second plurality of channel members over the second base portion, an isolation feature disposed between the first base portion and the second base portion, and a deep isolation structure in the substrate disposed below the isolation feature.