Nanosheet Corner Isolation Capping for Lower Parasitic Capacitance
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Solution Overview
Problem
Conventional nanosheet devices face high parasitic capacitance due to the thin isolation material between the metal gate and the semiconductor stack, which affects the performance of field-effect transistors (FETs).
Innovation Solution
A semiconductor capping layer made of the same material as the sacrificial semiconductor layer (e.g., silicon germanium) is used to protect the isolation structure during the removal of the dielectric isolation layer, resulting in a thicker isolation material and reduced parasitic capacitance, along with a more uniform inner spacer profile around the channel semiconductor layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the isolation material between the bottom portion of the semiconductor stack and the metal gate is made thin, then the device can be fabricated with simpler processes, but the parasitic capacitance between the metal gate and semiconductor stack increases
Solution Approach 1:
A capping layer is formed over the isolation structure before subsequent processing steps. This preliminary protective action ensures that the isolation structure maintains its thickness throughout fabrication, preventing the parasitic capacitance issue while allowing standard fabrication processes to proceed.
Solution Approach 2:
The capping layer acts as an intermediary protective element between the isolation structure and the etching/removal processes. It mediates the conflict by protecting the isolation material from being removed, thereby maintaining adequate thickness to reduce parasitic capacitance without complicating the fabrication process.
2Object-affected harmful factors
If the isolation material thickness is increased to reduce parasitic capacitance, then the capacitance between gate and semiconductor stack decreases, but the fabrication process becomes more complex
Solution Approach 1:
The capping layer is deposited in advance over the isolation structure, establishing protective coverage before any removal or modification steps. This preliminary action ensures the isolation thickness is preserved throughout the fabrication sequence, achieving low parasitic capacitance without adding significant process complexity.
Solution Approach 2:
The capping layer serves multiple functions: it protects the isolation structure from etching, provides a planar surface for subsequent processing, and maintains the electrical isolation properties. This multi-functionality achieves the capacitance reduction goal without proportionally increasing fabrication complexity.
3Ease of manufacture
If the dielectric isolation layer is completely removed to simplify the structure, then the manufacturing process is simplified, but the isolation structure thickness is reduced causing high parasitic capacitance
Solution Approach 1:
The capping layer serves as an intermediary protective barrier that allows selective removal of the dielectric isolation layer while preserving the isolation structure. It mediates between the need for process simplification (removing dielectric layer) and the need to maintain isolation thickness (preventing capacitance issues).
Solution Approach 2:
The capping layer is formed in advance to protect the isolation structure before the dielectric isolation layer removal step. This preliminary protective measure enables the simplification of removing the dielectric layer while ensuring the isolation structure thickness is maintained, preventing high parasitic capacitance.
Data Source
AI summary
Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a semiconductor stack including semiconductor layers over a substrate, wherein the semiconductor layers are separated from each other and are stacked up along a direction substantially perpendicular to a top surface of the substrate; an isolation structure around a bottom portion of the semiconductor stack and separating active regions; a metal gate structure over a channel region of the semiconductor stack and wrapping each of the semiconductor layers; a gate spacer over a source/drain (S/D) region of the semiconductor stack and along sidewalls of a top portion of the metal gate structure; and an inner spacer over the S/D region of the semiconductor stack and along sidewalls of lower portions of the metal gate structure and wrapping edge portions of each of the semiconductor layers.