Nanosheet Transistor Isolation via Dielectric Undercuts

Solution Overview

Problem

Current methods for isolating nanosheets on bulk substrates suffer from high leakage issues due to source/drain leakage through the substrate and result in increased defect formation and process complexity, particularly with high germanium concentration silicon germanium layers.

Innovation Solution

A method involving the formation of isolation regions using dielectric materials in undercut regions beneath nanosheet stacks, eliminating the need for high germanium concentration silicon germanium layers, thereby simplifying the isolation process and reducing defects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If high germanium concentration silicon germanium layers are used for isolation, then leakage is reduced, but defect formation increases and process complexity increases

Engineering Contradiction:

Improveleakage reductionVSAvoidprocess complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the isolation function from high germanium concentration silicon germanium layers and relocates it to dielectric material layers positioned between the nanosheet transistor and the bulk substrate. This removes the harmful complexity of processing high germanium layers while preserving the leakage reduction benefit through the dielectric isolation structure.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces dielectric material layers as an intermediary between the nanosheet transistor and the bulk substrate. These dielectric layers serve as the isolation medium, replacing the need for high germanium concentration silicon germanium layers and simplifying the overall process while maintaining effective leakage reduction.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If high germanium concentration silicon germanium layers are used for isolation, then leakage is reduced, but defect formation increases

Engineering Contradiction:

Improveleakage reductionVSAvoiddefect formation

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The patent extracts the isolation function from high germanium concentration silicon germanium layers and relocates it to dielectric material layers positioned between the nanosheet transistor and the bulk substrate. This removes the harmful complexity of processing high germanium layers while preserving the leakage reduction benefit through the dielectric isolation structure.

Inventive Principle:

Principle #2Taking out (Extraction)

3Device complexity

If nanosheets are formed on bulk substrate without isolation, then process complexity is reduced, but leakage increases

Engineering Contradiction:

Improveprocess complexityVSAvoidleakage

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The patent introduces dielectric material layers as an intermediary between the nanosheet transistor and the bulk substrate. These dielectric layers serve as the isolation medium, replacing the need for high germanium concentration silicon germanium layers and simplifying the overall process while maintaining effective leakage reduction.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS10461154B1Bottom isolation for nanosheet transistors on bulk substrate

Publication Date: 2019.10.29 SAMSUNG ELECTRONICS CO LTD

AI summary

A method of forming nanosheets that includes providing a stack of semiconductor material layers on a supporting bulk substrate. A first undercut region filled with a first dielectric material is formed extending from the opening into the bulk semiconductor substrate underlying the semiconductor material layers of the at least two stacks of semiconductor material layers. A second undercut region into the bulk semiconductor substrate filled with a second dielectric material from a side of the at least two stacks of semiconductor material layers that is opposite a side of the at least two stacks of semiconductor material layer at which the first undercut region is positioned. The first and second dielectric material merged that provide a full isolation region.