Nanosheet Isolation Protection Structure for Etch-Resistant GAA Transistors
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Solution Overview
Problem
Current manufacturing processes for nanosheet transistors, such as gate-all-around (GAA) transistors, face challenges in reducing current leakage and improving performance due to inadequate isolation features.
Innovation Solution
The formation of isolation units with upper portions doped with carbon and/or silicon, acting as isolation protection elements, to enhance resistance to etching processes, while lower portions remain undoped as isolation elements, thereby protecting the structure during manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If isolation features are formed to prevent current leakage among different transistors, then current leakage is reduced, but the isolation features may be damaged during subsequent etching processes
Solution Approach 1:
The isolation feature is divided into two distinct portions: a lower isolation portion that provides electrical isolation between transistors, and an upper isolation protection portion that protects the lower portion during etching processes. This segmentation allows each portion to be optimized for its specific function without compromise.
Solution Approach 2:
The upper isolation protection portion is formed over the lower isolation portion before subsequent etching processes occur. This preliminary protective structure is already in place to prevent damage to the lower isolation portion during manufacturing steps that follow.
2Strength
If the entire isolation feature is doped to enhance etching resistance, then etching resistance is improved, but current leakage protection may be compromised
Solution Approach 1:
Different portions of the isolation feature have different doping characteristics. The upper isolation protection portion can be doped to provide etching resistance, while the lower isolation portion maintains its undoped or differently doped state to ensure proper electrical isolation and prevent current leakage. Each region has localized properties optimized for its specific function.
3Productivity
If isolation features are made more robust to survive manufacturing processes, then manufacturing yield is improved, but transistor performance may deteriorate due to increased parasitic capacitance
Solution Approach 1:
By segmenting the isolation feature into upper and lower portions with different functions, the structure achieves robustness for manufacturing (upper portion) while maintaining performance (lower portion) through functional separation.
Solution Approach 2:
The upper isolation protection portion acts as an intermediary structure that absorbs the mechanical and chemical stress of manufacturing processes, shielding the lower isolation portion that is critical for transistor performance from damage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces current leakage and maintains the integrity of isolation features, leading to improved transistor performance and reduced parasitic capacitance by approximately 3%.
Implementation Method 1
performing an ion implantation process such that top portions of the isolation features are formed into isolation protection elements
Data Source
AI summary
A method for manufacturing a semiconductor structure includes: forming stacks each including a first nanosheet layer and a second nanosheet layer; forming isolation features among the stacks; performing an ion implantation process such that top portions of the isolation features are formed into isolation protection elements; forming a gate structure, each of the stacks having two portions that are located at two opposite sides of the gate structure; removing the two portions of each of the stacks to form source/drain recesses such that the first nanosheet layer, the second nanosheet layer, and the stacks are respectively formed into a first nanosheet, a second nanosheet, and patterned stacks; forming source/drain portions respectively in the source/drain recesses; removing a dummy gate of the gate structure; removing the second nanosheet of each of the patterned stacks; and forming a gate electrode around the first nanosheet of each of the patterned stacks.