Nanosheet Channel Isolation Using Dielectric Anchors and Oxide Fill
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing nanosheet fabrication processes face issues with the undesired etching of SiGe layers in the source and drain regions, leading to transistor failure, as the etching of sacrificial SiGe layers can affect the SiGe source and drain in pFET devices.
Innovation Solution
The process involves forming nanosheet fins with alternating silicon and silicon germanium layers, undercutting the SiGe layers to create divots, depositing a dielectric to anchor the silicon layers, and replacing the SiGe layers with an oxide matrix, which eliminates the need for SiGe removal during further fabrication steps, thereby avoiding the etching issues in the source and drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If sacrificial SiGe layers are etched between nanosheet stacks, then nanosheet formation is achieved, but SiGe layers in source and drain regions are undesirably etched causing transistor failure
Solution Approach 1:
The patent extracts and removes only the sacrificial SiGe layers located between the nanosheet stacks through selective etching, while preserving the SiGe layers in the source and drain regions. This selective removal enables proper nanosheet formation without compromising the structural integrity of the transistor's source and drain regions, thereby resolving the contradiction between manufacturing precision and device reliability
Solution Approach 2:
The patent applies different treatments to different regions of the device: the sacrificial SiGe layers between nanosheets are selectively removed to enable nanosheet formation, while the SiGe layers in source and drain regions are preserved to maintain transistor functionality. This localized differentiation of material properties and treatment approaches resolves the contradiction by ensuring each region receives the appropriate processing
2Manufacturing precision
If SiGe layers are removed to form nanosheets, then nanosheet structure is created, but mechanical anchoring of nanosheets is compromised
Solution Approach 1:
The patent introduces an intermediary material that provides mechanical anchoring for the nanosheets after the sacrificial SiGe layers are removed. This intermediary serves as a supporting structure that holds the nanosheets in place, resolving the contradiction between achieving proper nanosheet formation through SiGe removal and maintaining mechanical anchoring strength
Solution Approach 2:
The patent performs preliminary anchoring actions during the fabrication process, establishing mechanical support structures for the nanosheets before subsequent processing steps. This preliminary anchoring ensures that when sacrificial SiGe layers are removed, the nanosheets remain properly positioned and mechanically supported, preventing structural compromise
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures the mechanical anchoring of nanosheets with a dielectric and oxide replacement of SiGe layers, preventing the etching of SiGe in the source and drain regions, thus enhancing the reliability of nanosheet semiconductor devices by avoiding the failure of transistors.
Implementation Method 1
Depositing a dielectric at the first end and the second end includes depositing the dielectric in the divots at the first end and the second end
Implementation Method 2
the dielectric anchors the Si layers at the first end and the second end
Implementation Method 3
Removing the SiGe layers between the Si layers leaves gaps between the Si layers of each nanosheet stack
Data Source
AI summary
A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.