CMOS Nanosheet Source Drain Isolation via Oxide Barrier
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Solution Overview
Problem
Current CMOS nanosheet device fabrication techniques suffer from parasitic growth during epitaxy, leading to shorts between source and drain due to epitaxial growth on the underlying substrate.
Innovation Solution
A method involving the formation of alternating sacrificial and active channel nanosheets, followed by gate formation, spacer creation, lateral recessing, and epitaxial growth of source and drains from exposed tips of active channel nanosheets, with an oxide protective layer preventing substrate growth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If epitaxial growth is performed to form source and drain in CMOS nanosheet devices, then source and drain can be formed with good crystalline quality, but parasitic growth occurs on the underlying substrate causing shorts between source and drain
Solution Approach 1:
A sacrificial nanosheet layer is introduced as an intermediary between the substrate and the epitaxial growth region. This sacrificial layer prevents parasitic growth on the substrate while allowing controlled epitaxial growth from the active channel nanosheet tips. The sacrificial layer is later removed to complete the source-drain formation.
Solution Approach 2:
The sacrificial nanosheet layer is formed in advance before the epitaxial growth step. This preliminary action creates a protective barrier that prevents parasitic growth during the subsequent epitaxial process, ensuring that source and drain growth occurs only from the intended active channel nanosheet tips.
2Device complexity
If a single block mask is used for source and drain formation, then device fabrication complexity is reduced, but precise control of epitaxial growth locations becomes more difficult
Solution Approach 1:
The sacrificial nanosheet layer provides locally different properties: it protects the substrate in pocket regions while allowing epitaxial growth at the active channel nanosheet tips. This local differentiation enables precise control of epitaxial growth locations using a single block mask, as the sacrificial layer's presence or absence at different locations determines where growth occurs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively isolates source and drain, preventing shorts and enhancing the reliability of CMOS nanosheet devices by ensuring epitaxial growth occurs only from the active channel nanosheets, thereby improving device fabrication.
Implementation Method 1
The epitaxy growth process used to form the source and drains can cause parasitic growth on the underlying substrate
Implementation Method 2
laterally recessing the sacrificial nanosheets in the PFET and NFET stacks to expose tips of the active channel nanosheets
Implementation Method 3
epitaxially growing source and drains from the exposed tips of the active channel nanosheets sequentially in the PFET and NFET stacks
Data Source
AI summary
Techniques for source/drain isolation in nanosheet devices are provided. In one aspect, a method of forming a nanosheet device includes: forming an alternating series of sacrificial/active channel nanosheets as a stack on a substrate; forming gates on the stack; forming spacers alongside opposite sidewalls of the gates; patterning the stack, in between the spacers, into individual PFET/NFET stacks and pockets in the substrate; laterally recessing the sacrificial nanosheets in the PFET/NFET stacks to expose tips of the active channel nanosheets in the PFET/NFET stacks; forming inner spacers alongside the PFET/NFET stacks covering the tips of the active channel nanosheets; forming a protective layer lining the pockets; and selectively etching back the inner spacers to expose tips of the active channel nanosheets and epitaxially growing source and drains from the exposed tips of the active channel nanosheets sequentially in the PFET/NFET stacks. A nanosheet device is also provided.