Nanosheet Dielectric Isolation Structure for Void-Free Inner Spacers
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Solution Overview
Problem
In the manufacturing of nanosheet transistors, the formation of voids between inner spacers can lead to electric leakage due to larger side spaces compared to the spaces between nanosheets, particularly at the ends, which affects the integrity of source/drain regions.
Innovation Solution
A method involving the formation of a nanosheet stack with sacrificial sheets, a vertical dielectric pillar, and dielectric liners to create inner and side spacers, ensuring the side spacer thickness is equal to or less than the distance between nanosheets, and the distance between the nanosheet stack and the vertical pillar is adjusted to prevent void formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the space at the side of the nanosheets is made larger than the spaces between the nanosheets to enable formation of replacement gate stack, then the replacement gate stack can be fully formed, but voids are created surrounding the inner spacers causing electric leakage
Solution Approach 1:
A dielectric liner is introduced as an intermediary layer between the nanosheet stack and the vertical dielectric pillar. This liner fills the side space with a controlled thickness, preventing void formation while maintaining sufficient space for replacement gate stack formation. The liner acts as a mediator that resolves the conflict between needing space for manufacturing and preventing harmful voids.
Solution Approach 2:
The invention changes the dimensional parameters by controlling the thickness of the dielectric liner to be equal to or less than the distance between adjacent nanosheets. This parameter control ensures that the side spacer thickness is properly regulated, preventing void formation while maintaining the necessary space for gate stack formation.
2Reliability
If the distance between nanosheet stack and vertical pillar is adjusted to prevent void formation, then voids are eliminated, but the complexity of spacing control increases
Solution Approach 1:
The dielectric liner serves a dual function: it lines the nanosheet stack and vertical dielectric pillar while simultaneously controlling the side spacer thickness. This self-service approach simplifies the overall process by using a single structure to achieve multiple objectives, reducing the complexity of spacing control despite the precise dimensional requirements.
Data Source
AI summary
Embodiments of present invention provide a method of forming a nanosheet transistor structure. The method includes forming a nanosheet stack on a substrate, the nanosheet stack having a set of nanosheets separated by a set of sacrificial sheets; forming a vertical dielectric pillar separated from the nanosheet stack; forming a dielectric liner lining the nanosheet stack and the vertical dielectric pillar; forming a set of inner spacers between the set of nanosheets; forming a side spacer between the set of inner spacers and the vertical dielectric pillar, the side spacer being surrounded by the dielectric liner at least at a left side between the set of inner spacers and the side spacer and at a right side between the side spacer and the vertical dielectric pillar; and forming a replacement gate stack surrounding the set of nanosheets. A structure formed thereby is also provided.