Nanosheet LDMOS Field Plate Structure for Higher Breakdown Voltage
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Solution Overview
Problem
Fabricating semiconductor devices with higher performance and reliability while meeting smaller feature sizes is challenging, particularly for gate-controlled devices like MOS transistors that require high voltage operations, as maintaining good reliability and yield is difficult with conventional transistors.
Innovation Solution
The introduction of a nanosheet LDMOS transistor with a field plate dielectric layer in the drift region, which includes a thicker dielectric layer than the gate dielectric layer, enhances electrostatic control over the channel and drift region, improving on-state and off-state performance by reducing resistance and increasing breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional transistor structures are used for high voltage operations, then device simplicity is maintained, but reliability and performance deteriorate due to poor electrostatic control
Solution Approach 1:
The channel is divided into multiple thin nanosheet layers stacked vertically, creating multiple independent conduction paths. This segmentation improves electrostatic control by the gate over the channel region while maintaining high voltage operation capability, directly resolving the contradiction between reliability and structure complexity.
Solution Approach 2:
The transistor structure transitions from a planar two-dimensional channel to a three-dimensional stacked nanosheet configuration. This dimensional change enables superior gate control through the vertical stacking while accommodating high voltage requirements, addressing the reliability-structure complexity trade-off.
2Productivity
If feature sizes are reduced for higher performance, then device density improves, but manufacturing precision and yield worsen
Solution Approach 1:
The invention changes the channel geometry parameter from planar to vertically stacked nanosheets, achieving high device density without proportionally reducing lateral feature sizes. This parameter change allows improved productivity while maintaining manufacturing precision within existing fabrication capabilities.
3Reliability
If thicker dielectric layers are used in the drift region for better electrostatic control, then breakdown voltage increases, but device area increases
Solution Approach 1:
The drift region dielectric structure extends vertically through the stacked nanosheet configuration, achieving enhanced electrostatic control and higher breakdown voltage without increasing the lateral device footprint. This vertical dimension utilization resolves the contradiction between reliability and device area.
Data Source
AI summary
An integrated circuit includes a nanosheet laterally-diffused metal oxide semiconductor (LDMOS) transistor. The transistor includes source and drain regions having a first conductivity type that extend into a semiconductor substrate. A nanosheet region including semiconducting nanosheets extends between the source region and the drain region. A second dielectric layer on the nanosheets in a field plate region is thicker than a first dielectric layer on the nanosheets in a gate conductor region. The nanosheets alternate with gate conductor layers on the first dielectric in the gate conductor region which extends between the source region and a nanosheet dielectric spacer. The nanosheets alternate with field plate conductor layers on the second dielectric in the field plate region which extends between the drain region and the nanosheet dielectric spacer.