Nanosheet LDMOS Field Plate Layout for Lower Drift Resistance
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Solution Overview
Problem
Fabricating semiconductor devices with higher performance and reliability while meeting smaller feature sizes is challenging, particularly for gate-controlled devices like MOS transistors, which require improved electrostatic control and reduced resistance in high-voltage operations.
Innovation Solution
Incorporating field plates into nanosheet LDMOS transistors to enhance electric field uniformity and reduce source-drain resistance by distributing voltage drops more evenly across the drain drift region, using multiple field plates to achieve better electrostatic control and lower RDSON.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If field plates are added to nanosheet LDMOS transistors, then electrostatic control and electric field uniformity are improved, but device complexity increases
Solution Approach 1:
The transistor structure is segmented into multiple discrete field plates positioned at different locations along the drain drift region. Each field plate is independently formed and controlled, allowing selective placement to optimize electric field distribution without requiring complete structural redesign. This segmentation approach improves electrostatic control while managing complexity through modular addition.
Solution Approach 2:
Field plates are added in the lateral dimension along the drain drift region, extending the control architecture from the traditional gate-only approach to a multi-dimensional field control system. This dimensional expansion allows electric field uniformity to be improved by distributing control points across multiple spatial locations rather than relying on a single gate structure.
2Reliability
If multiple field plates are used to distribute voltage drops, then on-resistance is reduced, but manufacturing complexity increases
Solution Approach 1:
The voltage distribution function is segmented across multiple field plates rather than relying on a single continuous structure. Each field plate handles a specific segment of the drain drift region, collectively achieving uniform voltage distribution and reduced on-resistance. This segmentation allows standardized fabrication processes to be applied repeatedly across different regions.
Solution Approach 2:
The field plates serve multiple functions simultaneously: they provide electrostatic control, distribute voltage drops, and reduce on-resistance. By designing a single structural element that accomplishes multiple objectives, the manufacturing process is simplified compared to implementing separate structures for each function, thereby improving ease of manufacture while achieving the desired electrical performance.
3Productivity
If feature sizes are reduced for higher performance, then device density increases, but fabrication reliability deteriorates
Solution Approach 1:
As lateral feature sizes are reduced to increase device density, the patent introduces field plates that extend in the vertical dimension above the drain drift region. This vertical extension provides enhanced electrostatic control that compensates for the reduced lateral dimensions, maintaining fabrication reliability despite smaller feature sizes by adding a third-dimensional control mechanism.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The addition of field plates improves transistor performance by reducing on-resistance and increasing on-current, maintaining reliability and yield, and enabling efficient power technology scaling.
Implementation Method 1
Incorporating field plates into nanosheet LDMOS transistors to enhance electric field uniformity and reduce source-drain resistance by distributing voltage drops more evenly across the drain drift region
Data Source
AI summary
An integrated circuit includes a nanosheet laterally-diffused metal oxide semiconductor (LDMOS) transistor. The transistor includes source and drain regions having a first conductivity type that extend into a semiconductor substrate. A nanosheet region including semiconducting nanosheets extends between the source region and the drain region. The nanosheets alternate with gate conductor layers that extend between the source region and the drain region. The nanosheets also alternate with field plate conductor layers that extend between the gate conductor layers and the drain region.


