3D Nanosheet LDMOS Structure for Lower RDSON Scaling
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Solution Overview
Problem
Fabricating microelectronic devices with higher performance and smaller feature sizes while maintaining reliability and yield is challenging, especially for gate-controlled devices like MOS transistors that require high voltage operations, as scaling down can lead to increased parasitic resistance and capacitance.
Innovation Solution
The use of nanosheet LDMOS transistors with a superlattice structure of alternating semiconducting nanosheets, where the nanosheet region doping profile is optimized to reduce source-drain on-resistance (RDSON) by stacking multiple nanosheet ED transistors in three dimensions, and employing thicker nanosheets for high voltage applications to maintain electron mobility and achieve target specific on-resistance values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If feature size is scaled down to improve device integration, then device density increases, but parasitic resistance and capacitance increase leading to performance degradation
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional nanosheet structures. Multiple thin nanosheets are stacked vertically to form the channel region, enabling the device to utilize the third dimension (vertical stacking) rather than only lateral scaling. This dimensional transition allows continued scaling benefits while maintaining electrical performance by providing multiple parallel conduction paths through the stacked nanosheets.
Solution Approach 2:
The channel region is segmented into multiple discrete nanosheets stacked vertically, rather than using a single continuous planar channel. Each nanosheet acts as an independent conduction path, and the segmented structure allows for better control of electrical properties, reduced parasitic effects, and improved scalability compared to monolithic planar structures.
2Power
If voltage is increased for high voltage operations, then power handling capability improves, but electron mobility decreases due to scattering effects
Solution Approach 1:
The patent modifies the physical and electrical parameters of the channel structure by using ultrathin nanosheets with controlled thickness and doping profiles. By changing the dimensional parameters (reducing nanosheet thickness to nanometer scale) and electrical parameters (optimized doping concentrations), the device achieves high breakdown voltage capability while maintaining high electron mobility through reduced scattering mechanisms present in thicker structures.
Solution Approach 2:
The device employs composite material structures including alternating layers of semiconducting nanosheets and dielectric materials forming a superlattice. This composite structure combines the electrical conductivity of the nanosheets with the insulating properties of the dielectric layers, enabling high voltage operation while preserving electron transport properties through the conductive nanosheet channels.
Data Source
AI summary
Disclosed examples include microelectronic devices, e.g. Integrated circuits. One example includes a microelectronic device including a nanosheet lateral drain extended metal oxide semiconductor (LDMOS) transistor with source and drain regions having a first conductivity type extending into a semiconductor substrate having an opposite second conductivity type. A superlattice of alternating layers of nanosheets of a channel region and layers of gate conductor are separated by a gate dielectric, the superlattice extending between the source region and the drain region. A drain drift region of the first conductivity type extends under the drain region and a body region of the second type extends around the source region.