Nanoseheet Work Function Metal Patterning Undercut Reduction
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Solution Overview
Problem
The semiconductor industry faces challenges in lithographic patterning of nanosheet device features at production nodes below 10 nm, particularly in the formation of nanosheet FET devices, where etching operations can cause severe undercut of work function metal portions in adjacent channel structures, leading to inefficiencies and increased manufacturing costs.
Innovation Solution
A method involving the formation of stacked nanosheet channel structures with sacrificial regions, where channel regions are released and gate dielectric and work function metal layers are strategically blocked and removed to minimize undercutting, allowing for separate processing of N-type and P-type channel structures with different gate work function materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If etching operations are applied to release nanosheet layers of NFET device channel structure, then channel regions can be released for further processing, but severe undercut of work function metal portion of adjacent PFET device channel structure occurs
Solution Approach 1:
The patent segments the NFET and PFET processing into separate sequential operations. First, NFET channel regions are released by removing sacrificial regions while PFET work function metal is protected by a blocking layer. Then, PFET channel regions are released while NFET work function metal is protected. This segmentation prevents mutual undercutting during etching operations.
Solution Approach 2:
The patent applies preliminary protective action by forming a blocking layer over the PFET work function metal portion before performing the NFET sacrificial region removal etch. This preliminary protection prevents the etchant from attacking the PFET work function metal, thereby preventing undercut before it can occur.
2Manufacturing precision
If separate processing of N-type and P-type channel structures is implemented, then undercutting is reduced, but processing steps and device complexity increase
Solution Approach 1:
The patent divides the gate formation process into separate sequential operations for NFET and PFET devices. Each device type receives dedicated processing with appropriate protective blocking layers in place, allowing precise control over work function metal patterning without cross-contamination or undercutting from adjacent structures.
Solution Approach 2:
The patent introduces blocking layers as intermediary protective structures during etching operations. These blocking layers act as mediators that prevent the etchant from directly contacting and undercutting the work function metal portions of adjacent device types, enabling separate processing while maintaining overall process integration.
Data Source
AI summary
A semiconductor structure comprises a semiconductor substrate, an N-type stacked nanosheet channel structure formed on the semiconductor substrate, and a P-type stacked nanosheet channel structure formed adjacent to the N-type stacked nanosheet channel structure on the semiconductor substrate. Each of the adjacent N-type and P-type stacked nanosheet channel structures comprises a plurality of stacked channel regions with each such channel region being substantially surrounded by a gate dielectric layer and a gate work function metal layer, and with the gate work function metal layer being separated from the channel regions by the gate dielectric layer. The gate dielectric and gate work function metal layers of the adjacent N-type and P-type stacked nanosheet channel structures are substantially eliminated from a shared gate region between the adjacent N-type and P-type stacked nanosheet channel structures.