Nanosheet MOSFET Source/Drain Sidewalls for Lower Parasitic Capacitance

The patent transitions from conventional planar (2D) transistor structures to three-dimensional nanosheet and FinFET structures. The nanosheets are suspended above the substrate in a third dimension, creating a vertical channel that increases the effective channel area without increasing the footprint. This dimensional transition reduces parasitic capacitance by increasing the channel-gate overlap area while maintaining compact device footprint, directly addressing the technical contradiction between device performance and parasitic effects.

The gate structure completely surrounds the nanosheet channel in a wrap-around configuration, with the gate extending over the top surface and down the sidewalls of the nanosheet. This nested arrangement maximizes the gate-controlled channel area while minimizing the distance between gate and channel, thereby reducing parasitic resistance and improving carrier control without requiring larger device dimensions.

By utilizing vertical suspension of nanosheets above the substrate and extending gates in the vertical dimension, the patent achieves higher effective channel area per unit footprint. This allows increased integration density while maintaining adequate gate control and minimizing parasitic capacitance, as the vertical dimension provides additional control volume without increasing lateral device dimensions that would increase parasitic effects.

The patent implements different structural qualities in different regions: suspended nanosheets with air gaps in active device regions to minimize parasitic capacitance, while maintaining continuous substrate and isolation structures in interconnect regions. The gate structure provides enhanced local control over the channel with wrap-around geometry, creating locally optimized regions that collectively achieve high integration density with controlled parasitic effects.

The patent achieves increased gate-channel overlap area by extending the gate structure into the vertical dimension, wrapping around the suspended nanosheet channel. The gate overlaps the channel from the top surface down the sidewalls, creating a three-dimensional overlap volume that increases the effective overlap area without increasing the lateral footprint of the device. This vertical extension allows parasitic capacitance reduction while maintaining compact device dimensions.

The wrap-around gate structure nests over and around the nanosheet channel, with the gate material conformally covering the channel sidewalls and top surface. This nested configuration maximizes the gate-channel overlap area within the minimal lateral space required by the nanosheet width, thereby reducing parasitic capacitance without increasing device footprint beyond the nanosheet dimensions.