Nanosheet MOSFET Structure for High-Density IC Scaling Limits
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Solution Overview
Problem
As integration density of integrated circuit devices increases, the scaling of devices has reached its limit, requiring a change in device structure to improve performance and provide transistors with various characteristics.
Innovation Solution
An integrated circuit device is designed with fin-type active regions and a nano-sheet stacked structure, featuring semiconductor layers with a semiconductor interface, and gate electrodes that extend across these regions, allowing for multi-gate metal-oxide-semiconductor field-effect transistors (MOSFETs) in both cell and peripheral circuit regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device scaling continues to increase integration density, then integration density is improved, but device performance deteriorates due to reaching scaling limits
Solution Approach 1:
The patent transitions from planar 2D transistor structures to three-dimensional multi-gate structures (FinFET and nanosheet configurations). The FinFET uses a vertically extending fin structure with a gate wrapping around three sides, while the nanosheet structure employs horizontally stacked semiconductor sheets with gates enclosing multiple surfaces. This dimensional transition increases the effective channel area and gate control without further lateral scaling, thereby improving device performance while maintaining high integration density.
Solution Approach 2:
The semiconductor channel is segmented into multiple discrete structures: vertically segmented fins in FinFET devices and horizontally stacked nanosheets in nanosheet FETs. Each segment provides an independent conduction path controlled by the gate, effectively multiplying the total channel width and drive current capability within a compact footprint, thus enhancing performance without increasing overall device area.
2Reliability
If device structure is changed to improve performance, then device performance is improved, but device complexity increases
Solution Approach 1:
The patent develops universal multi-gate transistor structures that can be implemented in both cell regions and peripheral circuit regions of integrated circuits. The FinFET and nanosheet FET designs serve multiple functions: they provide high-performance switching in logic circuits, enable compact integration in dense arrays, and support various semiconductor materials (Si, Ge, III-V compounds) for different device characteristics. This multi-functionality allows a single structural approach to address diverse performance requirements across different circuit blocks, managing complexity through design universality.
Solution Approach 2:
The gate structure is nested around the semiconductor channel in a wrap-around configuration. In FinFETs, the gate envelops the vertical fin on three sides; in nanosheet FETs, the gate surrounds the stacked sheets from multiple directions. This nested geometry provides maximum gate control over the channel with minimal additional process complexity, as the same deposition and etching techniques used for planar gates can be adapted to create the wrapped structures through conformal coating and anisotropic removal.
Data Source
AI summary
Provided is an integrated circuit device including: a plurality of fin-type active regions protruding from a top surface of a substrate and extending in a first horizontal direction; at least one semiconductor layer, each including a lower semiconductor layer and an upper semiconductor layer sequentially stacked on at least one of the plurality of fin-type active regions; and a plurality of gate electrodes extending in a second horizontal direction crossing the first horizontal direction on the plurality of fin-type active regions, wherein the lower semiconductor layer includes a same material as a material of the upper semiconductor layer, and wherein a semiconductor interface is provided between the lower semiconductor layer and the upper semiconductor layer.