Nanosheet MOSFET Separation Wall Geometry for Scaled IC Performance
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Solution Overview
Problem
As the degree of integration of integrated circuit devices increases, device size is minimized, and scaling reaches a limitation, necessitating new methods to enhance device performance, particularly through modifications in device structure.
Innovation Solution
The development of an integrated circuit device featuring a multi-gate metal-oxide-semiconductor field-effect transistor (MOSFET) with a specific structure, including a base substrate layer, sheet separation walls, nanosheet stack structures, source/drain regions, and gate electrodes, which enhances operation characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device size is reduced to increase integration degree, then integration density is improved, but device performance deteriorates due to scaling limitations
Solution Approach 1:
The patent transitions from planar 2D transistor structures to three-dimensional multi-gate structures (tri-gate, tetra-gate, or penta-gate configurations). By stacking nanosheets vertically and wrapping gate electrodes around them, the invention utilizes the third dimension (vertical stacking) to increase effective channel area and gate control without increasing the planar footprint, thereby maintaining high integration density while improving device performance through enhanced electrostatic control and drive current.
2Reliability
If multi-gate structure is implemented to enhance performance, then device performance is improved, but manufacturing complexity increases
Solution Approach 1:
The patent divides the transistor structure into discrete, modular components: individual nanosheets stacked vertically, separate gate electrodes wrapping around different portions of the nanosheets, and distinct source/drain regions. This segmentation allows each component to be formed through specialized process steps (e.g., selective epitaxial growth for nanosheets, sequential gate formation), simplifying the manufacturing of complex multi-gate structures compared to attempting to form them as monolithic structures.
Solution Approach 2:
The patent implements gate electrodes that wrap around nanosheets in a nested configuration, with gate electrodes positioned at different vertical levels surrounding the nanosheet stack. Inner gate electrodes are positioned closer to the nanosheet core, while outer gate electrodes surround them at greater radial distances. This nested arrangement enables multi-gate control while using standard semiconductor fabrication techniques for forming concentric or layered structures.
3Manufacturing precision
If sheet separation wall has convex round portion to improve fabrication, then manufacturing precision is improved, but device area increases
Solution Approach 1:
The patent applies the convex round portion feature locally and selectively to specific regions of the sheet separation wall, particularly at corners or edges where stress concentration or fabrication difficulties occur during etching or deposition processes. The straight portions of the sheet separation wall are maintained in critical areas where precise dimensional control is essential for device performance. This localized application of geometric modification optimizes fabrication yield without unnecessarily increasing the overall device footprint.
Data Source
AI summary
An integrated circuit device includes a base substrate layer, a sheet separation wall extending in a first horizontal direction on the base substrate layer, a pair of nanosheet stack structures spaced apart from each other with the sheet separation wall therebetween in a second horizontal direction different from the first horizontal direction, the pair of nanosheet stack structures each including a plurality of nanosheets, a pair of source/drain regions spaced apart from each other with the sheet separation wall therebetween in the second horizontal direction, wherein the pair of source/drain regions are electrically connected to the pair of nanosheet stack structures, respectively, and a pair of gate electrodes extending in the second horizontal direction on the pair of nanosheet stack structures, wherein opposing side surfaces of the sheet separation wall in the second horizontal direction include a round portion having a convex shape between the pair of source/drain regions.