Nanosheet Gate Pinch-Off Layout for Multi-Vt Channel Integration

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Solution Overview

Problem

Current semiconductor device fabrication techniques face challenges in achieving multiple threshold voltages for nanosheet transistors due to limited space between channel nanosheets, making it difficult to perform patterning steps for work function metal deposition and removing organic planarization layers without pinching off.

Innovation Solution

The method involves forming air gaps or pinch-off regions between gate structures around nanosheet channel regions, allowing for selective doping and tuning of threshold voltages by controlling gate metal deposition, dopant type, and doping process conditions, eliminating the need for additional patterning schemes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If work function metal patterning is performed to achieve multiple threshold voltages, then threshold voltage control is improved, but device complexity and fabrication difficulty increase due to limited space between nanosheets

Engineering Contradiction:
Improvethreshold voltage controlVSAvoidfabrication process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent extracts the work function metal patterning step from the fabrication process by using air gaps to define regions where work function metal will be deposited. Instead of performing complex patterning operations in the limited space between nanosheets, the air gaps pre-establish the spatial boundaries for subsequent metal deposition, eliminating the need for additional patterning steps while maintaining precise threshold voltage control.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent performs preliminary action by forming air gaps between gate structures before work function metal deposition. These air gaps serve as pre-defined regions that guide where work function metal will be deposited, allowing threshold voltage tuning without requiring complex in-situ patterning operations. The air gaps are formed in advance to facilitate subsequent selective metal deposition.

Inventive Principle:
Principle #10Preliminary action

2Adaptability or versatility

If organic planarization layers are removed to access nanosheet regions, then fabrication flexibility is improved, but risk of pinching off and structural damage increases

Engineering Contradiction:
Improvefabrication flexibilityVSAvoidstructural integrity
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent uses air gaps as intermediary structures that provide access to nanosheet regions without requiring removal of organic planarization layers. The air gaps serve as mediators that allow subsequent processing steps to reach the nanosheet regions while maintaining the structural integrity of the planarization layers, thus preserving both fabrication flexibility and structural reliability.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Adaptability or versatility

If additional patterning schemes are implemented for work function metal deposition, then threshold voltage tuning capability is improved, but manufacturing complexity and process time increase

Engineering Contradiction:
Improvethreshold voltage tuning capabilityVSAvoidfabrication throughput
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent makes the air gap structure multi-functional by using it both as a physical separator between gate structures and as a template for work function metal deposition. This single structure performs multiple functions: defining gate boundaries, controlling threshold voltage regions, and guiding metal deposition patterns. This eliminates the need for separate patterning schemes, maintaining threshold voltage tuning capability while improving fabrication throughput.

Inventive Principle:
Principle #6Universality (Multi-functionality)

4Area of moving object

If space between nanosheets is reduced to increase device density, then device density is improved, but ability to perform patterning steps and remove planarization layers deteriorates

Engineering Contradiction:
Improvedevice densityVSAvoidfabrication accessibility
Core Design Contradiction:
Area of moving objectVSEase of manufacture

Solution Approach 1:

The patent solves the space constraint by introducing air gaps in the vertical dimension between gate structures, rather than requiring horizontal space between nanosheets. This dimensional approach allows patterning and processing access without increasing the footprint or reducing nanosheet spacing, maintaining high device density while preserving fabrication accessibility.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables separate tuning of threshold voltages for nanosheet transistors without requiring additional work function metal patterning, achieving co-integration of fabrication processes across multiple substrate regions and selective control of threshold voltages.

Implementation Method 1

A dopant is applied to the first gate structure and the second gate structure, wherein the dopant is configured to enter the air gap and penetrate into the first gate structure and the second gate structure from within the air gap.

Methodology Applied
Scientific EffectDiffusion: Diffusion

Data Source

PatentUS11830877B2Co-integrated channel and gate formation scheme for nanosheet transistors having separately tuned threshold voltages
Publication Date: 2023.11.28 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US11830877B2 patent drawing
  • US11830877B2 patent drawing
  • US11830877B2 patent drawing

AI summary

Embodiments of the invention are directed to a configuration of nanosheet FET devices in a first region of a substrate. Each of the nanosheet FET devices in the first region includes a first channel nanosheet, a second channel nanosheet over the first channel nanosheet, a first gate structure around the first channel nanosheet, and a second gate structure around the second channel nanosheet, wherein the first gate structure and the second gate structure pinch off in a pinch off area between the first gate structure and the second gate structure. The first gate structure includes a doped region, and the second gate structure includes a doped region. At least a portion of the pinch off area is undoped.