Nanosheet PMOS Channel Engineering With Germanium Cladding
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Solution Overview
Problem
As semiconductor devices continue to scale down, there is a need for further improvements in nanosheet FETs to enhance device density, performance, and reduce costs, while addressing challenges in fabrication and design, particularly in achieving better gate control and reducing short-channel effects.
Innovation Solution
The method involves forming a stack of semiconductor layers with alternating materials, patterning fin structures, and using a sacrificial gate structure to create nanosheet channels, followed by a germanium cladding layer to enhance carrier mobility, where germanium atoms are diffused into the silicon channel layers through thermal treatment to form silicon germanium channel layers, and a gate electrode is formed around these layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor dimensions are scaled down to increase device density, then production efficiency and cost are improved, but gate control and short-channel effects deteriorate
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional nanosheet channels where the gate electrode completely surrounds the channel in all directions (top, bottom, and sidewalls). This wrap-around gate configuration provides superior electrostatic control over the channel, effectively suppressing short-channel effects that plague scaled-down transistors while maintaining high device density.
Solution Approach 2:
The patent employs alternating semiconductor layers with different materials properties (e.g., silicon channels with silicon germanium barrier layers) to create nanosheet FETs. This composite structure enables better gate control through material engineering, where the different semiconductor materials provide complementary functions for channel conduction and gate isolation, addressing the reliability challenges of miniaturized devices.
2Reliability
If nanosheet FET structures are implemented to improve gate control, then short-channel effects are reduced, but fabrication complexity increases
Solution Approach 1:
The patent divides the channel region into multiple discrete nanosheets separated by electrically isolated barrier layers. This segmentation approach creates independent conduction paths that can be individually controlled by the gate, improving short-channel effects while the modular structure allows for systematic fabrication processes that manage complexity through repetition of standardized layers.
Solution Approach 2:
The patent forms the complete alternating stack of semiconductor and barrier layers using epitaxial growth before any gate or contact fabrication steps. This preliminary formation of the nanosheet structure establishes the three-dimensional channel geometry early in the process, enabling subsequent gate electrodes to be deposited around pre-formed channels, thereby simplifying the overall fabrication sequence despite the complex final structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves carrier mobility and short-channel control for PMOS transistors, maintaining sheet-to-sheet spacing and reducing interface scattering, thereby enhancing device performance and efficiency.
Implementation Method 1
germanium atoms are diffused into the silicon channel layers through thermal treatment to form silicon germanium channel layers
Implementation Method 2
germanium atoms are diffused into the silicon channel layers through thermal treatment
Data Source
AI summary
Embodiments provide a method for forming a semiconductor device structure, includes forming a fin structure having first semiconductor layers and second semiconductor layers alternatingly stacked thereover, forming a sacrificial gate structure over a portion of the fin structure, removing portions of the sacrificial gate structure to expose the first and second semiconductor layers, removing portions of the second semiconductor layers to expose portions of each of the first semiconductor layers. The method includes surrounding the exposed portions of each of the first semiconductor layers with a cladding layer, wherein the cladding layer is formed of a material chemically different from the first semiconductor layers, and the cladding layer has a first atomic percentage of germanium. The method includes performing a thermal treatment so that germanium atoms of the cladding layer are diffused into and reacted with the first semiconductor layer to form an intermixed layer, wherein the intermixed layer has a second atomic percentage of germanium that is less than the first atomic percentage of germanium. The method includes forming a gate electrode layer to surround each of the intermixed layers.