Nanosheet and Vertical P-N-P Diode Integration With Bottom Isolation
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Solution Overview
Problem
Existing semiconductor technologies face challenges in integrating ideal vertical P-N-P diodes with bottom dielectric isolation and logic/static random access memory (SRAM) devices in a cost-effective and simple manner, while maintaining robustness and area efficiency.
Innovation Solution
The integration of gate-all-around nanosheet devices with bottom dielectric isolation and ideal vertical P-N-P diodes on a common substrate is achieved by forming P-N-P vertical implanted layers and a nanosheet device with a bottom dielectric isolation layer, using a gate-last approach and selective etching to define implant doses and energies, and optionally incorporating a dielectric isolation ring to prevent surface degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If lateral P-N-P diodes are used instead of vertical structures, then device formation is simpler, but robustness and area efficiency deteriorate
Solution Approach 1:
The patent inverts the conventional lateral P-N-P diode structure by implementing a vertical P-N-P configuration. The P-substrate, N-well, and P-implant layers are stacked vertically rather than laterally, which restores the robustness and area efficiency characteristics while maintaining compatibility with standard CMOS fabrication processes through sequential implantation steps
2Reliability
If ideal vertical P-N-P diodes are integrated with bottom dielectric isolation logic/SRAM devices, then device robustness and area efficiency are improved, but integration complexity and fabrication cost increase
Solution Approach 1:
The patent merges the formation of P-N-P vertical implanted layers for the diode with the nanosheet device fabrication process. The P-substrate, N-well, and P-implant layers are formed using the same ion implantation and epitaxial growth steps that create the nanosheet device structures, allowing both device types to share a common fabrication flow without requiring separate processing lines
Solution Approach 2:
The P-N-P vertical implanted layers serve dual functions: they form the ideal vertical P-N-P diode structure in the first region while simultaneously providing the doping profile and structural foundation for the nanosheet devices in the second region. This multi-functionality reduces the total number of fabrication steps and eliminates the need for additional dedicated processing for diode formation
3Reliability
If bottom dielectric isolation layer is used, then source-to-drain leakage is prevented, but device formation complexity increases
Solution Approach 1:
The patent extracts the bottom dielectric isolation layer from the nanosheet device region by selectively removing it, creating a defined isolation structure. This is achieved through selective etching processes that remove the dielectric material beneath the nanosheet channels while leaving it intact in other regions, thereby preventing source-to-drain leakage without requiring complex additional isolation structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method facilitates the easy and effective co-integration of nanosheet devices with ideal vertical P-N-P diodes, preserving implant layers and preventing source-to-drain leakage, while maintaining device robustness and efficiency.
Implementation Method 1
the diode includes P-N-P vertical implanted layers present in the bulk substrate
Implementation Method 2
a single source/drain region epitaxial material disposed on the P-N-P vertical implanted layers
Data Source
AI summary
Techniques for co-integrating gate-all-around nanosheet devices having bottom dielectric isolation with an ideal vertical P-N-P diode on a common substrate are provided. In one aspect, a semiconductor structure includes: a diode in a first region of a bulk substrate, where the diode includes P-N-P vertical implanted layers present in the bulk substrate, and a single source/drain region epitaxial material disposed on the P-N-P vertical implanted layers; and a nanosheet device with a bottom dielectric isolation layer in a second region of the bulk substrate. The nanosheet device can include nanosheet channels and gates that surround a portion of each of the nanosheet channels in a gate-all-around configuration. A method of fabricating the present semiconductor structures is also provided.