Nanosheet Power Bar Layout for Backside Power Connections

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Solution Overview

Problem

Nanosheet technology faces challenges in scaling down due to device interference and difficulty in forming connections to a backside power network as devices become smaller and closer together.

Innovation Solution

A semiconductor device structure with a power bar oriented parallel to nanodevices, connected to source/drain contacts through dielectric liners, and extending to a backside power rail, facilitating connections between nanodevices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If nanosheet devices are scaled down and placed closer together, then device density is improved, but device interference increases and connection formation becomes more difficult

Engineering Contradiction:
Improvedevice densityVSAvoidconnection formation difficulty
Core Design Contradiction:
Quantity of substanceVSEase of manufacture

Solution Approach 1:

The patent introduces a power bar structure that extends in a lateral dimension between adjacent nanosheet devices, providing a new spatial pathway for power connections. This lateral extension allows connections to be formed without increasing vertical complexity, accommodating higher device density while maintaining manufacturability through planar integration.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The power bar acts as an intermediary structure between source/drain contacts and the backside power network. By introducing this intermediate conductive element, the patent simplifies the connection architecture, enabling power distribution to densely packed nanosheet devices without requiring direct complex routing between each contact and the power network.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Area of stationary object

If devices are placed closer together, then area utilization is improved, but forming connections to backside power network becomes more difficult

Engineering Contradiction:
Improvearea utilizationVSAvoidconnection formation difficulty
Core Design Contradiction:
Area of stationary objectVSEase of manufacture

Solution Approach 1:

The power bar extends laterally between devices in the plane of the substrate, utilizing the horizontal dimension to provide connection pathways. This approach maintains compact vertical stacking for high area utilization while creating adequate lateral space for power connection formation without increasing overall device footprint.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The power distribution network is segmented into discrete power bar elements positioned between specific nanosheet devices. Each power bar serves as an independent connection segment, allowing localized optimization of connection formation while maintaining overall high device density and area utilization.

Inventive Principle:
Principle #1Segmentation

3Length of stationary object

If power connections are made with higher aspect ratio, then vertical integration is improved, but resistance increases

Engineering Contradiction:
Improvevertical integrationVSAvoidconnection resistance
Core Design Contradiction:
Length of stationary objectVSReliability

Solution Approach 1:

The power bar provides a lateral conduction pathway that reduces the effective current path length compared to purely vertical connections. By extending horizontally between devices, the power bar creates a lower aspect ratio conduction path that maintains vertical integration benefits while reducing resistance through increased lateral spread and reduced current density.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12550714B2Late middle-of-line gate cut with power bar formation
Publication Date: 2026.02.10 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US12550714B2 patent drawing
  • US12550714B2 patent drawing
  • US12550714B2 patent drawing

AI summary

According to the embodiment of the present invention, a semiconductor device includes a first nanodevice comprised of a plurality of first transistors and a second nanodevice comprised of a plurality of second transistors. The first nanodevice includes a first source/drain contact. The second nanodevice includes a second source/drain contact. The second nanodevice is located adjacent to and parallel to the first nanodevice. A power bar is located between the first nanodevice and the second nanodevice. The power bar is connected to the second source/drain contact. A top surface of the power bar and the second source/drain contact are substantially in a same plane. The top surface of the power bar and the second source/drain contact are substantially a same height.