Nanosheet Gate Structure with Recessed Inner Spacer for Channel Control
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Solution Overview
Problem
Existing integrated circuit devices face challenges in achieving higher integration and improved performance while efficiently designing wiring structures to enhance functions and operating speeds.
Innovation Solution
The integrated circuit device incorporates a fin-type active region with a nanosheet stack, a gate line comprising a main and sub-gate part, and an inner insulating spacer with recessed sidewalls and varying thicknesses to optimize the channel region and source/drain regions, utilizing materials like silicon nitride and silicon oxide for enhanced insulation and contact areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional planar transistor structure is used, then the device structure is simple and easy to manufacture, but the integration capacity and operating speed are limited
Solution Approach 1:
The patent transitions from a conventional planar transistor structure to a three-dimensional structure featuring vertical nanosheet stacks and a wraparound gate line that extends over the top surface of the nanosheet stack. This dimensional change enables higher integration capacity by utilizing vertical space while maintaining manufacturability through standard semiconductor processing techniques adapted for 3D structures.
Solution Approach 2:
The gate line is segmented into multiple portions: a first gate portion wrapping around the nanosheet stack and a second gate portion extending on the top surface. This segmentation allows independent optimization of each gate region for different functions (channel control and additional drive current), resolving the contradiction between integration density and structural simplicity.
2Reliability
If the gate line completely surrounds the nanosheet stack, then the channel control is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The gate line provides more than 360 degrees of coverage around the nanosheet stack by extending onto the top surface, creating an 'excessive' wraparound structure. This partial extension beyond the minimal surrounding requirement enhances channel control through increased gate authority while remaining compatible with conventional manufacturing processes that can accommodate the extended geometry without requiring ultra-precise alignment.
3Ease of manufacture
If the inner insulating spacer has uniform thickness, then the manufacturing process is simpler, but the contact area with source/drain regions is reduced
Solution Approach 1:
The inner insulating spacer is designed with non-uniform thickness, featuring a first thickness in the vertical direction and a second thickness (greater than the first) in the horizontal direction at the interfaces with source/drain regions. This local thickening at critical contact interfaces improves electrical contact reliability and reduces resistance, while the overall spacer structure remains compatible with standard manufacturing processes using selective deposition and etching techniques.
4Stability of the object's composition
If the sidewalls of the inner insulating spacer are vertical, then the structural stability is maintained, but the contact area with channel region is limited
Solution Approach 1:
The sidewalls of the inner insulating spacer are designed with recessed portions that create curved or angled interfaces with the channel region, rather than purely vertical walls. This curvature increases the contact surface area between the insulating spacer and the channel, improving electrical characteristics and reliability, while the overall spacer structure maintains sufficient structural stability through the recessed geometry that distributes mechanical stresses.
Data Source
AI summary
An integrated circuit device may include a nanosheet stack including a plurality of nanosheets, a gate line at least partially surrounding each of the plurality of nanosheets, the gate line including a main gate part and a sub-gate part, a source/drain region in contact with the plurality of nanosheets, and an inner insulating spacer between the sub-gate part and the source/drain region, wherein a first sidewall and a second sidewall each include a part recessed toward an inside of the inner insulating spacer, the first sidewall facing the source/drain and the second sidewall opposite to the first sidewall.


