Nanosheet Replacement Metal Gate Patterning for N/P Boundary Control
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Solution Overview
Problem
Conventional nanosheet patterning techniques are limited in achieving precise dimensions and boundary control between n-type and p-type FET devices, particularly in dense logic and SRAM regions, where the patterning boundary cannot effectively extend to open FETs, leading to inefficiencies in device performance.
Innovation Solution
The method involves a Replacement Metal Gate (RMG) approach where a base device with nanosheet stacks is fabricated, followed by deposition of an organic planarizing layer, patterning to expose nanosheet stacks, removing bottom gate material and work function metal in doped regions, and depositing a second work function material to form a gate-all-round structure, allowing for extended patterning boundaries and improved n/p boundary control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If standard immersion lithography techniques are used for patterning nanosheets, then the manufacturing process is simple and well-established, but the critical dimensions (device width) that can be printed are limited and precise n/p boundary control cannot be achieved
Solution Approach 1:
The patterning process is divided into multiple stages: initial nanosheet stack formation, organic planarizing layer deposition, selective patterning to expose nanosheet stacks, and subsequent metal gate formation. This segmentation allows each stage to address specific requirements, achieving precise n/p boundary control without requiring a complete overhaul of the manufacturing process
Solution Approach 2:
The organic planarizing layer is deposited and patterned in advance to define the boundaries before metal gate formation. This preliminary patterning action establishes the n/p boundaries that guide subsequent processing steps, enabling precise control without adding significant complexity to the overall process
2Reliability
If the patterning boundary is extended to open FETs, then device performance is improved, but the manufacturing process becomes more complex and difficult to control
Solution Approach 1:
The organic planarizing layer serves as an intermediary that simplifies the extension of patterning boundaries to open FETs. By using this removable organic layer as a temporary mask and boundary-defining structure, the process achieves extended patterning coverage without directly exposing the complexity of boundary extension to the metal gate formation step
3Reliability
If bottom gate material is removed in doped regions to form gate-all-round structures, then device performance is enhanced, but the manufacturing process steps increase and productivity may be reduced
Solution Approach 1:
The removal of bottom gate material and formation of gate-all-round structures is merged with the metal gate formation process. The same patterning and deposition steps that create the metal gates also remove the bottom gate material in doped regions, achieving multiple objectives in a unified process sequence rather than separate steps
Data Source
AI summary
A device includes a base layer structure including a first region and a second region; a first bottom gate material in a plurality of first-type doped regions in the first and second regions; a second bottom gate material in a second-type doped regions in the first and second regions; first nanosheet gate-all-round device structures on the first bottom gate material; and second nanosheet gate-all-round device structures on the second bottom gate material, wherein the first bottom gate material is located over the second nanosheet gate-all-around device structures in the second-type doped regions of the first and second regions, wherein the second bottom gate material extends, in boundary regions between the first-type and second-type doped regions, on the base layer structure from the second nanosheet gate-all-around devices structures toward the first gate-all-round device structures.