Nanosheet ROM Cell Layout for Lower Off-Current and Smaller Area
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Solution Overview
Problem
Existing semiconductor storage devices face challenges with increased off-current due to excessive scaling, leading to higher power consumption, and there is a lack of examination on the layout structure of mask ROM using nanosheet FETs and forksheet FETs.
Innovation Solution
A semiconductor storage device layout structure is proposed, utilizing first and second nanosheet FETs with fork-shaped gate electrodes, where the nanosheets are opposed to each other, and their faces closer to each other are exposed from the gate interconnects, reducing the distance between the nanosheets and thereby minimizing the area of the semiconductor storage device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional planar transistors are used with scaling, then integration degree and operating speed are improved, but off current increases and power consumption increases
Solution Approach 1:
The patent transitions from conventional planar two-dimensional transistor structures to three-dimensional nanosheet FET structures. The nanosheet channel is formed as a thin film extending in the vertical dimension, allowing the gate electrode to wrap around and control the channel from multiple directions. This dimensional change enables better electrostatic control and reduced off-current while maintaining high integration density.
2Speed
If gate length is scaled down, then operating speed is improved, but off current increases significantly
Solution Approach 1:
The nanosheet FET structure enables the gate electrode to extend in the vertical dimension and wrap around the channel region. This three-dimensional gate configuration provides enhanced electrostatic control over the channel, allowing for shorter gate lengths that improve operating speed while maintaining low off-current through superior field effect control.
Solution Approach 2:
The gate electrode is configured to surround the nanosheet channel from multiple directions, with the gate wrapping around the channel region in a nested configuration. This multi-directional gate control provides enhanced electrostatic management of the channel, enabling reduced off-current even at scaled dimensions.
3Area of stationary object
If nanosheet FETs with fork-shaped gate electrodes are used, then area is reduced, but layout complexity increases
Solution Approach 1:
Adjacent nanosheet FETs share common gate interconnect structures and power supply lines. The fork-shaped gate electrodes of neighboring devices are integrated into unified interconnect patterns, and power supply lines are routed to serve multiple devices simultaneously. This merging approach reduces overall layout complexity while achieving compact area utilization.
Solution Approach 2:
The gate interconnect structures are designed to serve multiple functions: they provide gate control for individual nanosheet FETs while also forming shared power supply lines and interconnect pathways for adjacent devices. This multi-functional design reduces the number of separate structures needed, simplifying the overall layout despite the three-dimensional nanosheet configuration.
Data Source
AI summary
In a semiconductor storage device, a first ROM cell includes a first nanosheet FET having a first nanosheet as the channel region, provided between a first bit line and a first ground power supply line. A second ROM cell includes a second nanosheet FET having a second nanosheet as the channel region, provided between a second bit line and a second ground power supply line. The face of the first nanosheet closer to the second nanosheet in the X direction is exposed from a first gate interconnect, and the face of the second nanosheet closer to the first nanosheet in the X direction is exposed from a second gate interconnect.