Nanosheet SAC Structure With Backside Gate Contact
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Solution Overview
Problem
Current nanosheet transistors face issues with large parasitic capacitance between the metal gate and self-aligned source/drain contact, leading to yield and reliability problems due to corner erosion of the self-aligned contact cap.
Innovation Solution
A method is developed to fabricate a nanosheet transistor with a dielectric nanosheet on top, forming self-aligned contacts to the source/drain region and a gate contact on the wafer backside, which reduces parasitic capacitance and enhances the robustness of the self-aligned contact by using a dielectric nanosheet to enable a metal gate only at the nanosheet level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a metal gate is positioned at the nanosheet level, then gate control over the channel is improved, but parasitic capacitance between the gate and self-aligned contact increases
Solution Approach 1:
The gate contact is moved from the top surface to the backside of the substrate, utilizing the third dimension (depth/vertical position) to spatially separate the gate contact from the self-aligned contact. This dimensional repositioning eliminates the parasitic capacitance issue while preserving the gate's control function over the nanosheet channel.
Solution Approach 2:
The substrate acts as an intermediary barrier that electrically isolates the gate contact from the self-aligned contact. By routing the gate contact through the substrate backside, the substrate serves as a natural dielectric medium that prevents direct electrical coupling between the gate and source/drain contacts, thereby eliminating parasitic capacitance.
2Reliability
If a self-aligned contact cap is formed over the gate, then contact protection is improved, but corner erosion occurs leading to yield problems
Solution Approach 1:
The contact cap structure is completely removed from the gate area. Instead of forming a cap over the gate that suffers from corner erosion, the invention extracts this problematic element and replaces it with a backside gate contact approach, eliminating the source of manufacturing defects while maintaining contact protection through alternative means.
Solution Approach 2:
Instead of protecting the contact by capping it from the top (conventional approach), the invention inverts the protection strategy by forming the gate contact from the backside of the substrate. This inversion eliminates the need for a top-side contact cap that is susceptible to corner erosion during fabrication processes.
3Ease of manufacture
If conventional top-side contact formation is used, then fabrication process is simple, but parasitic capacitance and contact cap erosion problems occur
Solution Approach 1:
The fabrication process is extended into the vertical dimension by accessing the substrate backside for gate contact formation. While this adds a wafer flip step, it eliminates the need for complex contact cap structures and their associated corner erosion issues, as well as removing parasitic capacitance, resulting in net process simplification despite the additional orientation change.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a thicker self-aligned contact cap, improving device performance, reducing power consumption, and minimizing parasitic capacitance between the metal gate and source/drain region.
Implementation Method 1
Nanosheet formation relies on the selective removal of one semiconductor material (e.g., silicon) to another semiconductor material (e.g., a silicon germanium alloy) to form suspended nanosheets for gate-all-around devices.
Implementation Method 2
Source/drain (S/D) regions for nanosheet containing devices are currently formed by epitaxial growth of a semiconductor material upwards from an exposed surface of the semiconductor substrate and from sidewalls of each nanosheet.
Data Source
AI summary
Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A nanosheet stack of alternating nanosheets of a sacrificial semiconductor material nanosheet and a semiconductor channel material nanosheet and a dielectric nanosheet as a top layer of the nanosheet stack is provided above a semiconductor substrate. A dummy gate with a gate cap and spacers on the sidewalls straddle over the nanosheet stack. End portions of the sacrificial semiconductor material nanosheets are recessed. A dielectric spacer material layer is formed. A source/drain region is formed on the sidewalls of each semiconductor channel material nanosheet. The dummy gate and gate cap are removed. Each sacrificial semiconductor material nanosheet is removed. A functional gate structure is formed that wraps around each suspended semiconductor channel material nanosheet. A self-aligned source/drain contact region is formed. A gate contact region is formed in a trench in the semiconductor substrate.