Nanosheet S/D Bottom Isolation With Air Gaps for Leakage Control
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Solution Overview
Problem
Nanosheet transistors face challenges such as current leakage between source/drain and substrate, high parasitic capacitance due to physical connection of S/D features with inner spacers, and less gate control in bottom single gate devices, leading to performance issues.
Innovation Solution
An isolation layer is formed on the bottom surface of the S/D trench to prevent substrate contact, and air gaps are created between S/D features and the substrate and inner spacers, allowing S/D features to be epitaxially grown only from channel semiconductor layers, reducing parasitic capacitance and leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If S/D features are epitaxially grown from substrate and channel semiconductor layers, then device structure is formed, but leakage path occurs between S/D and substrate causing current leakage
Solution Approach 1:
The patent segments the S/D feature formation process by introducing an air gap that divides the continuous epitaxial growth path into separate regions. The S/D feature is grown only from the channel semiconductor layer, while the substrate is isolated by the air gap, preventing direct electrical connection and eliminating the leakage path.
Solution Approach 2:
The air gap acts as an intermediary barrier between the S/D feature and the substrate. This intermediate space physically separates the two regions, preventing direct contact and the formation of leakage paths while still allowing the device structure to be formed through controlled epitaxial growth from the channel layer.
2Ease of manufacture
If S/D features physically connect inner spacers surrounding metal gate, then device structure is formed, but high parasitic capacitance occurs between S/D features and metal gate
Solution Approach 1:
The patent extracts the harmful physical connection between S/D features and inner spacers by introducing an air gap. This separation removes the source of parasitic capacitance while preserving the essential device structure, allowing the S/D features to be formed through epitaxial growth without direct contact to the spacers.
Solution Approach 2:
The air gap serves as an intermediary that prevents direct physical contact between the S/D features and the inner spacers. This intermediate space eliminates the parasitic capacitance pathway while still allowing the device to function, as the separation is achieved through controlled growth processes rather than complete isolation.
3Device complexity
If bottom single gate device is formed with less gate control, then device structure is simplified, but high leakage occurs due to insufficient gate control
Solution Approach 1:
The patent segments the gate control region by introducing an air gap that separates the bottom single gate structure from the substrate. This segmentation improves gate control over the channel by preventing unwanted electrical interactions with the substrate, thereby reducing leakage current while maintaining a relatively simple gate structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively mitigates bulk leakage current and parasitic capacitance, enhancing the performance of nanosheet transistors by ensuring the S/D features are isolated from the substrate and inner spacers, thereby improving device speed and reducing leakage.
Implementation Method 1
an isolation layer is formed on the bottom surface of the S/D trench. The isolation layer prevents direct contact between the source/drain features and the substrate, thereby reducing bulk leakage current
Implementation Method 2
Air gaps are also formed between the source/drain features and the substrate. This approach effectively mitigates bulk leakage current and parasitic capacitance
Implementation Method 3
S/D features are epitaxially grown only from channel semiconductor layers
Data Source
AI summary
Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises first semiconductor stack over a substrate, wherein the first semiconductor stack includes first semiconductor layers separated from each other and stacked up along a direction substantially perpendicular to a top surface of the substrate; second semiconductor stack over the substrate, wherein the second semiconductor stack includes second semiconductor layers separated from each other and stacked up along the direction substantially perpendicular to the top surface of the substrate; inner spacers between edge portions of the first semiconductor layers and between edge portions of the second semiconductor layers; and a bulk source/drain (S/D) feature between the first semiconductor stack and the second semiconductor stack, wherein the bulk S/D feature is separated from the substrate by a first air gap, and the bulk S/D feature is separated from the inner spacers by second air gaps.