Nanosheet Transistor Source/Drain Depth Layout for Short-Channel Control
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Solution Overview
Problem
Current semiconductor devices face challenges in improving element performance and reliability, particularly in scaling techniques for increasing density and suppressing short channel effects in multi gate transistors.
Innovation Solution
The semiconductor device incorporates a unique design with multiple active patterns and gate structures, including first and second active patterns with specific spacings and source/drain patterns, featuring different gate electrode and insulating film configurations to enhance performance and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi gate transistor scaling is performed to increase density, then device density is improved, but short channel effects worsen
Solution Approach 1:
The patent implements a multi-gate transistor structure where gate electrodes wrap around the channel region in three dimensions, transitioning from planar 2D gate control to 3D multi-dimensional gate control. This dimensional change allows the gate to control the channel from multiple directions (top, bottom, and sides), effectively suppressing short channel effects while maintaining scaled dimensions and increasing device density.
2Reliability
If gate length is increased to suppress short channel effects, then reliability is improved, but device density worsens
Solution Approach 1:
Instead of increasing gate length in one dimension, the patent uses multi-gate structures that provide control from multiple dimensions (top, bottom, sides). This allows effective channel control with shorter gate lengths, maintaining high device density while suppressing short channel effects through three-dimensional gate geometry rather than extended one-dimensional gate length.
3Reliability
If different gate structures are used for first and second active patterns, then element performance is improved, but device complexity increases
Solution Approach 1:
The patent applies different gate configurations to different active patterns based on their specific performance requirements. The first active pattern receives first gate structures with specific spacing and dimensions, while the second active pattern receives second gate structures with different spacing and dimensions. This local differentiation optimizes element performance for each pattern while maintaining overall device functionality.
Solution Approach 2:
The patent divides the semiconductor device into multiple active patterns (first and second active patterns) with distinct gate structures. This segmentation allows independent optimization of gate parameters for different regions, enabling tailored performance characteristics for each active pattern while managing complexity through modular design.
Data Source
AI summary
A semiconductor device comprising a first active pattern including a first lower pattern, and a plurality of first sheet patterns, a plurality of first gate structures on the first lower pattern, a second active pattern including a second lower pattern and a plurality of second sheet patterns, a plurality of second gate structures on the second lower pattern, a first source/drain recess between adjacent first gate structures, a second source/drain recess between adjacent second gate structures, first and second source/drain patterns in the first and second source/drain recesses, respectively, wherein a depth from an upper surface of the first lower pattern to a lowermost part of the first source/drain pattern is smaller than a depth from an upper surface of the second lower pattern to a lowermost part of the second source/drain pattern, and the first and second source/drain patterns include impurities of same conductive type.