Nanosheet Semiconductor Device With Multi-Gate Current Control
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Solution Overview
Problem
Current semiconductor devices face challenges in scaling density and controlling current without increasing gate length, while effectively suppressing short channel effects, particularly in multi-gate transistors with three-dimensional channels.
Innovation Solution
The semiconductor device incorporates a specific layout and structure with active patterns, nanosheets, and gate electrodes arranged in a particular configuration, where the pitch and width of field insulating layers and gate electrodes are optimized to improve current control and reliability, with at least part of the gate electrode covering the sidewalls of nanosheets in the PMOS region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-gate transistors with three-dimensional channels are used to increase density, then scaling capability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The device divides the channel into multiple nanosheets (first, second, third, fourth nanosheets) stacked vertically, creating a multi-gate structure. This segmentation allows the channel to be controlled by multiple gate electrodes from different directions, improving current control capability and suppressing short channel effects while maintaining scalability
Solution Approach 2:
The patent transitions from planar two-dimensional channel structures to three-dimensional stacked nanosheet structures. The nanosheets are arranged vertically with gates wrapping around them, creating a multi-gate configuration that exploits the third dimension to improve device performance and density without proportionally increasing manufacturing complexity
2Reliability
If gate length is increased to improve current control, then current control capability is improved, but device area increases
Solution Approach 1:
The patent uses vertically stacked nanosheets with multiple gate electrodes wrapping around them from different directions. This three-dimensional multi-gate configuration provides superior current control capability compared to increasing gate length, as the gates control the channel from multiple angles without requiring additional horizontal or vertical length, thereby maintaining compact device footprint
3Productivity
If pitch between active patterns is reduced to increase density, then device density is improved, but short channel effects worsen
Solution Approach 1:
The channel is segmented into multiple thin nanosheets stacked vertically, with each nanosheet controlled by gates from multiple directions. This segmentation allows closer spacing of active patterns in the horizontal direction while the vertical stacking and multi-gate configuration maintain effective channel control, suppressing short channel effects even at reduced pitches
Solution Approach 2:
The patent applies different pitch values in different regions: a first pitch in the first horizontal direction between adjacent nanosheets, and a second pitch in the second horizontal direction. This anisotropic pitch configuration allows dense packing in one direction while maintaining sufficient spacing in the other direction to prevent short channel effects, optimizing both density and reliability
Data Source
AI summary
A semiconductor device includes first to fourth active patterns extending in a horizontal first direction. The second active pattern is spaced apart from the first active pattern in the first direction. The third active pattern is spaced apart from the first active pattern in a horizontal second direction. The fourth active pattern is spaced apart from the third active pattern in the first direction. A field insulating layer surrounds a sidewall of each of the first to fourth active patterns. First to fourth pluralities of nanosheets are respectively disposed the first to fourth active patterns. A first gate electrode extends in the second direction, intersects each of the first and third active patterns, and surrounds the first and third pluralities of nanosheets. A second gate electrode extends in the second direction, intersects each of the second and fourth active patterns, and surrounds the second and fourth pluralities of nanosheets.