Nanosheet Source/Drain Facet Structure for Lower Contact Resistance

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Solution Overview

Problem

The challenge in integrated circuit devices is to enhance the performance and reliability of nanosheet field-effect transistors by reducing contact resistance and improving the distribution of electrical characteristics as devices scale down.

Innovation Solution

The integrated circuit device incorporates a fin-type active region with nanosheets and a source/drain region comprising a lower and upper main body layer, where the lower facet and upper facet intersect, and the source/drain region is formed in a recess, with specific Ge concentrations and orientations to enhance strain and uniformity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the integration density of integrated circuit devices is increased and the size is decreased, then the miniaturization and integration are improved, but the contact resistance of source/drain region increases and electrical characteristics distribution deteriorates

Engineering Contradiction:
Improveintegration densityVSAvoidcontact resistance
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The source/drain region is segmented into multiple layers (lower main body layer and upper main body layer) with different materials and properties. The lower main body layer is formed in a recess of the fin-type active region, while the upper main body layer is formed on the lower main body layer, creating a multi-layered structure that reduces contact resistance through optimized material composition and strain distribution in each layer

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the source/drain structure are given different local qualities: the lower main body layer has specific material composition (e.g., SiGe with higher Ge concentration) to provide strain and reduce contact resistance, while the upper main body layer has different composition (e.g., SiGe with lower Ge concentration or pure Si) to maintain crystal quality and reduce defects. The facets of these layers are oriented at specific angles to optimize strain distribution locally

Inventive Principle:
Principle #3Local quality

2Quantity of substance

If the integration density of integrated circuit devices is increased and the size is decreased, then the miniaturization and integration are improved, but the electrical characteristics distribution deteriorates

Engineering Contradiction:
Improveintegration densityVSAvoidelectrical characteristics distribution
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The source/drain region is divided into multiple layers with different material compositions and structural characteristics. This segmentation allows each layer to be optimized for specific functions: the lower main body layer provides strain and contact resistance reduction, while the upper main body layer maintains crystal quality, resulting in more uniform electrical characteristics across the device

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The material parameters (composition, concentration) and geometric parameters (layer thickness, facet angles) are changed and optimized for each layer. The lower main body layer may have higher Ge concentration and specific facet orientation, while the upper main body layer has different parameters, creating a gradient structure that improves electrical characteristics distribution

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration reduces contact resistance and improves the electrical characteristics distribution, leading to increased reliability and performance of the integrated circuit device.

Implementation Method 1

the lower main body layer and an upper main body layer, the lower and upper main body layers being sequentially stacked on the fin-type active region in the vertical direction, wherein a top surface of the lower main body layer includes a lower facet declining toward the substrate as it extends in a direction from the at least one nanosheet to a center of the source/drain region

Methodology Applied
Scientific EffectStrain: Deformation

Data Source

PatentUS12396224B2Integrated circuit device
Publication Date: 2025.08.19 SAMSUNG ELECTRONICS CO LTD
  • US12396224B2 patent drawing
  • US12396224B2 patent drawing
  • US12396224B2 patent drawing

AI summary

An integrated circuit device includes a fin-type active region on a substrate; at least one nanosheet having a bottom surface facing the fin top; a gate line on the fin-type active region; and a source/drain region on the fin-type active region, adjacent to the gate line, and in contact with the at least one nanosheet, wherein the source/drain region includes a lower main body layer and an upper main body layer, a top surface of the lower main body layer includes a lower facet declining toward the substrate as it extends in a direction from the at least one nanosheet to a center of the source/drain region, and the upper main body layer includes a bottom surface contacting the lower facet and a top surface having an upper facet. With respect to a vertical cross section, the lower facet extends along a corresponding first line and the upper facet extends along a second line that intersects the first line.