Nanosheet Source/Drain Isolation via Segmented Epitaxial Growth
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Solution Overview
Problem
Nanosheet devices face source/drain shorts and parasitic leakage due to epitaxially grown doped regions in recessed portions of semiconductor substrates, which necessitate improved isolation techniques.
Innovation Solution
A method involving the formation of silicon germanium and silicon layers in a stacked configuration, patterning to create recessed portions, etching of silicon germanium layers, and growth of inner spacer layers followed by epitaxial source/drain regions to prevent shorts and leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If epitaxially grown doped source/drain regions are formed in recessed portions of semiconductor substrate, then source/drain regions can be formed adjacent to nanosheet structures, but source/drain shorts and parasitic leakage occur through parasitic channel portions under the gates
Solution Approach 1:
The source/drain structure is segmented into two distinct parts: (1) lower epitaxial layers grown in recessed portions of the substrate, and (2) epitaxial source/drain regions grown from the lateral sides of nanosheet channel structures. This segmentation allows each part to serve a specific function while maintaining electrical isolation through undoped or counter-doped intermediate regions.
Solution Approach 2:
Different doping conditions are applied to different spatial locations: the lower epitaxial layers in recessed portions are grown with undoped or counter-doped conditions to prevent parasitic conduction, while the epitaxial source/drain regions adjacent to channel structures are properly doped for carrier injection. This local quality differentiation resolves the contradiction between forming conductive source/drain regions and preventing parasitic leakage.
2Productivity
If stacked nanosheet structures are used to enable CMOS scaling, then superior electrostatics and higher current density per footprint area are achieved, but source/drain shorts and parasitic leakage occur due to inadequate isolation
Solution Approach 1:
The isolation strategy extends into the vertical dimension by forming lower epitaxial layers in recessed portions of the substrate beneath the nanosheet structures. This vertical dimension approach, combined with lateral isolation through undoped regions, creates a three-dimensional isolation architecture that prevents parasitic conduction paths while maintaining the high current density benefits of stacked nanosheets.
3Device complexity
If silicon germanium layers are selectively removed to form nanosheet and GAA structures, then desired device structures are formed, but additional etching steps are required to remove exposed lateral sides of silicon germanium layers
Solution Approach 1:
Inner spacer layers are formed in advance during the nanosheet structure fabrication process, specifically after selective removal of silicon germanium layers but before final source/drain formation. This preliminary action of forming inner spacers protects the nanosheet structures and defines precise locations for subsequent epitaxial growth, eliminating the need for additional protective measures or complex alignment steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents source/drain shorts and reduces parasitic leakage by forming undoped or counter-doped lower epitaxial regions under source/drain areas, enhancing electrical isolation in nanosheet structures.
Implementation Method 1
the silicon germanium layers are etched to remove portions of the silicon germanium layers from exposed lateral sides of each of the silicon germanium layers
Implementation Method 2
A plurality of lower epitaxial layers are grown in the plurality of recessed portions in a first epitaxial growth process
Implementation Method 3
A plurality of epitaxial source/drain regions are grown from the plurality of lower epitaxial layers and from exposed lateral sides of the silicon layers in a second epitaxial growth process
Data Source
AI summary
A method for manufacturing a semiconductor device includes forming a plurality of silicon germanium and silicon layers on a semiconductor substrate in a stacked configuration comprising a repeating arrangement of a silicon layer stacked on a silicon germanium layer. The stacked configuration is patterned into a plurality of patterned stacks spaced apart from each other. The patterning forms a plurality of recessed portions in the substrate. In the method, the silicon germanium layers are etched to remove portions of the silicon germanium layers from exposed lateral sides of the silicon germanium layers, and inner spacer layers are formed in place of the removed portions. A plurality of lower epitaxial layers are grown in the recessed portions. A plurality of epitaxial source/drain regions are grown from the lower epitaxial layers and from exposed lateral sides of the silicon layers.