Nanosheet Source Drain Epitaxy Using Sacrificial Layer Isolation

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Solution Overview

Problem

The miniaturization of transistors and semiconductor devices poses challenges in the growth of source and drain regions, leading to impaired growth and increased current leakage due to tighter pitches, which compromises transistor performance.

Innovation Solution

A method involving the formation of a sacrificial layer on both sides of a stack of nanosheets with a dummy gate structure, allowing for the growth of source and drain regions from the sacrificial layer and ends of the nanosheets, followed by the removal of the sacrificial layer and deposition of an interlevel dielectric to improve isolation and reduce current leakage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If transistor size is reduced to increase device density, then device integration is improved, but source and drain region growth is impaired

Engineering Contradiction:
Improvedevice integrationVSAvoidsource and drain region growth
Core Design Contradiction:
ProductivityVSEase of manufacture

Solution Approach 1:

A sacrificial layer is introduced as an intermediary structure between the substrate and the source/drain regions. This sacrificial layer provides a growth template that enables proper source and drain region formation even in miniaturized devices, after which it is removed to achieve the final compact structure.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The sacrificial layer is formed in advance before source and drain region growth. This preliminary structure facilitates the epitaxial growth process by providing a suitable surface and geometry, ensuring proper region formation before the sacrificial material is removed.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If pitch is reduced to increase device density, then device integration is improved, but current leakage increases

Engineering Contradiction:
Improvedevice integrationVSAvoidcurrent leakage
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The sacrificial layer is selectively removed after serving its growth facilitation purpose. This extraction creates isolation structures that prevent current leakage paths between adjacent miniaturized devices, allowing tight pitch while maintaining electrical isolation.

Inventive Principle:
Principle #2Taking out (Extraction)

3Productivity

If device size is reduced to improve integration, then device density is improved, but isolation quality deteriorates

Engineering Contradiction:
Improvedevice densityVSAvoidisolation quality
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The sacrificial layer serves as a mediator that enables the formation of isolation structures. By providing a removable template, it allows for the creation of proper isolation regions between source and drain even when device dimensions are reduced, maintaining isolation quality in high-density configurations.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the growth quality and isolation of source and drain regions, leading to more efficient and reliable semiconductor devices with reduced parasitic losses and improved performance, enabling smaller device sizes without compromising reliability.

Implementation Method 1

Source and drain regions are grown on from the sacrificial layer and from ends of the second nanosheets

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Data Source

PatentUS11495688B2Source and drain epitaxy and isolation for gate structures
Publication Date: 2022.11.08 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US11495688B2 patent drawing
  • US11495688B2 patent drawing
  • US11495688B2 patent drawing

AI summary

Semiconductor devices and methods for forming the semiconductor devices include forming a sacrificial layer on a substrate on each side of a stack of nanosheets, the stack of nanosheets including first nanosheets and second nanosheets stacked in alternating fashion with a dummy gate structure formed thereon. Source and drain regions are grown on from the sacrificial layer and from ends of the second nanosheets to form source and drain regions in contact with each side of the stack of nanosheets. The sacrificial layer is removed. An interlevel dielectric is deposited around the source and drain regions to fill between the source and drain regions and the substrate.