GAA IC Structure With Backside Source Via for Leakage Reduction
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing low-cost, high-performance, and low-power integrated circuits due to increased complexity from scaling down semiconductor IC dimensions, which affects the efficiency and cost of the manufacturing process.
Innovation Solution
The development of gate-all-around (GAA) transistor structures with backside vias below source regions, utilizing multi-gate transistors and nanosheet channels, allows for improved electrostatic control and reduced leakage currents, enabling more efficient routing space and manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor IC dimensions are scaled down to improve production efficiency and lower costs, then manufacturing productivity increases, but manufacturing process complexity increases
Solution Approach 1:
The patent transitions from planar 2D transistor structures to three-dimensional structures including FinFETs with vertical fins and gate-all-around (GAA) nanosheet channels. This dimensional change enables continued scaling by exploiting the vertical dimension, improving electrostatic control and device performance while maintaining manufacturability through established fabrication processes adapted for 3D geometries.
Solution Approach 2:
The gate structure completely surrounds the channel region in GAA transistors, with multiple nanosheet channels stacked vertically and each surrounded by the gate. This nested configuration provides maximum electrostatic control over the channel while maintaining a manufacturable structure using sequential deposition and etching processes.
2Ease of manufacture
If conventional planar transistors are used, then manufacturing process is simpler, but electrostatic control of channel is insufficient and leakage currents increase
Solution Approach 1:
The invention introduces vertical fins in FinFET structures and fully three-dimensional gate-all-around configurations surrounding nanosheet channels. This dimensional transition provides superior electrostatic control over the channel region compared to planar devices, reducing off-state leakage currents while maintaining compatibility with extended drain structures for stress engineering.
Solution Approach 2:
The patent employs composite material structures including semiconductor fins or nanosheets surrounded by gate dielectric and gate electrode materials, with extended drain regions using different semiconductor compositions. This composite approach optimizes electrostatic control, carrier mobility, and stress management simultaneously.
Data Source
AI summary
A method for manufacturing an integrated circuit (IC) structure is provided. The method includes: etching a first recess and a second recess in a substrate; forming a sacrificial epitaxial plug in the first recess in the substrate; forming a first epitaxial feature and a second epitaxial feature respectively in the first recess and the second recess, wherein the first epitaxial feature is over the sacrificial epitaxial plug; forming a first source/drain epitaxial structure and a second source/drain epitaxial structure over the first epitaxial feature and the second epitaxial feature respectively; forming a gate structure laterally between the first source/drain epitaxial structure and the second source/drain epitaxial structure; removing the sacrificial epitaxial plug and the first epitaxial feature to form a backside via opening exposing a backside of the first source/drain epitaxial structure; and forming a backside via in the backside via opening.