Nanosheet Transistor Spacer Structure for Gate-Source Isolation
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Solution Overview
Problem
It is challenging to isolate gate metals from source/drain regions in nanosheet transistors while maintaining desired electrical characteristics.
Innovation Solution
The use of a low-K second dielectric layer between the cap metal and the source/drain contact, along with a first dielectric spacer layer between the gate metal and the source/drain contact, reduces parasitic capacitance and improves electrical isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional transistors are used with standard isolation structures, then manufacturing is simpler, but parasitic capacitance between gate metal and source/drain regions increases, degrading electrical performance
Solution Approach 1:
The isolation structure is segmented into multiple functional layers: a first dielectric layer providing primary isolation between gate metal and source/drain regions, and a second dielectric layer providing additional isolation and planarization. This segmentation allows each layer to be optimized for its specific function, achieving superior electrical isolation without excessive overall complexity.
Solution Approach 2:
Dielectric layers are introduced as intermediary materials between conductive elements (gate metal and source/drain regions). These intermediary layers act as electrical insulators that prevent parasitic capacitance formation while maintaining the necessary spatial relationships between components.
2Reliability
If dielectric spacer layers are added between gate metal and source/drain contact, then parasitic capacitance is reduced, but manufacturing complexity increases
Solution Approach 1:
The first dielectric layer is formed preliminarily during the gate stack formation process, before source/drain region definition. This preliminary action establishes the isolation structure early in the fabrication sequence, allowing subsequent processing steps to build upon this foundation without requiring additional complex isolation-specific steps.
Solution Approach 2:
The dielectric constant (K value) of the second dielectric layer is specifically optimized to provide appropriate electrical isolation characteristics. By selecting materials with appropriate dielectric constants, the structure achieves effective parasitic capacitance reduction while maintaining compatibility with standard fabrication processes.
3Productivity
If nanosheet transistor dimensions are reduced to increase density, then computing power increases, but isolation between gate metal and source/drain regions becomes more difficult to maintain
Solution Approach 1:
The isolation problem is solved by transitioning from two-dimensional planar isolation to three-dimensional multi-layer isolation. The stacked dielectric layers provide isolation in the vertical dimension, enabling effective electrical separation even as horizontal dimensions are scaled down to increase transistor density.
Solution Approach 2:
The isolation structure uses composite dielectric materials with different properties: the first dielectric layer provides primary isolation, while the second dielectric layer provides additional isolation and planarization. This composite approach allows optimization of each layer's thickness and material properties to maintain effective isolation at reduced dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration results in faster switching of transistor states and improved electrical signal characteristics by reducing parasitic capacitance between the source/drain contacts and the cap metal.
Implementation Method 1
reduces parasitic capacitance and improves electrical isolation
Data Source
AI summary
An integrated circuit includes a nanosheet transistor having a plurality of stacked channels, a gate electrode surrounding the stacked channels, a source/drain region, and a source/drain contact. The integrated circuit includes a first dielectric layer between the gate metal and the source/drain contact, a second dielectric layer on the first dielectric layer, and a cap metal on the first gate metal and on a hybrid fin structure. The second dielectric layer is on the hybrid fin structure between the cap metal and the source/drain contact.