Nanosheet Transistor Spacer Layout for Uniform Junction Formation
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Solution Overview
Problem
The challenge in nanosheet transistor fabrication lies in achieving uniformity and precision in spacer formation, particularly in the 7 nm node and beyond, where conventional methods like spacer RIE and timed etch lead to junction variations and material loading effects, affecting the performance and density of integrated circuits.
Innovation Solution
A method involving a vertical stack of nanosheet channel layers with alternating sacrificial silicon germanium layers, where a dielectric dummy gate is formed, oxidized, and epitaxial source/drain regions are grown, followed by the deposition of a dielectric liner and the removal of sacrificial layers to create spaces, allowing for the formation of gate dielectric and metal gate without conventional spacer RIE or timed etch, enabling concurrent outer spacer and interlevel dielectric liner formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional spacer RIE and timed etch methods are used, then spacer formation can be achieved, but junction uniformity deteriorates and material loading effects occur
Solution Approach 1:
The patent applies preliminary action by forming a dummy gate structure before the actual gate, using it as a template for spacer formation. The dummy gate is formed at a first time, spacers are formed based on it, then the dummy gate is removed and replaced with the actual gate. This preliminary structure enables precise spacer formation without direct etching of the final gate, eliminating junction uniformity issues.
Solution Approach 2:
The dummy gate serves as an intermediary element that mediates between the fabrication process and the final gate structure. It acts as a temporary placeholder that enables spacer formation through deposition rather than etching, avoiding material loading effects. After spacers are formed, the dummy gate is removed and replaced with the functional gate.
2Manufacturing precision
If separate processes are used for outer spacers and interlevel dielectric liners, then each structure can be optimized, but fabrication complexity increases
Solution Approach 1:
The patent merges the formation of outer spacers and interlevel dielectric liners into a single concurrent deposition process. Both structures are formed simultaneously using the same dummy gate as a reference, eliminating the need for separate fabrication processes. This reduces fabrication complexity while maintaining the structural optimizations of both components.
Solution Approach 2:
The dummy gate serves multiple functions: it acts as a template for outer spacer formation, a reference for interlevel dielectric liner deposition, and eventually is replaced by the functional gate. This multi-functional use of a single structure simplifies the overall fabrication process while enabling precise formation of multiple critical components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances junction uniformity and allows for the same material to be used for outer spacers, inner spacers, and interlevel dielectric liners, improving the fabrication process for nanosheet transistors, particularly in tight pitch applications like the 7 nm node, by eliminating the need for conventional spacer RIE and timed etch, thereby reducing junction variations and improving device performance.
Implementation Method 1
The first and second lateral edge portions are oxidized such that first oxide layers and second oxide layers are formed from the first lateral edge portions and the second lateral edge portions, respectively
Implementation Method 2
Source/drain regions are epitaxially grown on the nanosheet channel layers
Data Source
AI summary
Inner and outer spacers for nanosheet transistors are formed using techniques that improve junction uniformity. One nanosheet transistor device includes outer spacers and an interlevel dielectric layer liner made from the same material. A second nanosheet transistor device includes outer spacers, inner spacers and an interlevel dielectric layer liner that are all made from the same material.