Nanosheet Transistor Spacer Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
It is challenging to isolate gate metals from source/drain regions in nanosheet transistors while maintaining desired electrical characteristics, leading to issues with parasitic capacitance and switching speeds in integrated circuits.
Innovation Solution
The use of a low-K dielectric spacer layer between the gate metal and source/drain contacts, along with a cap metal extending across hybrid fin structures to connect gate metals, reduces parasitic capacitance and improves electrical signal transmission by replacing high-K dielectric materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-K dielectric materials are used between gate metal and source/drain contacts, then electrical isolation is improved, but parasitic capacitance increases and switching speed decreases
Solution Approach 1:
The patent changes the dielectric constant parameter from high-K to low-K materials in the spacer layers between gate metal and source/drain contacts. This parameter change reduces parasitic capacitance while maintaining electrical isolation, thereby improving switching speed without sacrificing reliability.
Solution Approach 2:
The patent introduces low-K dielectric spacer layers as intermediary structures between the gate metal and source/drain contacts. These spacer layers act as mediators that provide electrical isolation while minimizing parasitic capacitance, thus resolving the contradiction between isolation and switching speed.
2Area of stationary object
If gate metal is placed close to source/drain regions, then device area is reduced, but parasitic capacitance increases
Solution Approach 1:
The patent introduces low-K dielectric spacer layers as intermediary structures between the gate metal and source/drain regions. These spacers enable closer placement of gate metal to source/drain regions (reducing area) while simultaneously providing electrical isolation (reducing parasitic capacitance).
Solution Approach 2:
The patent changes the dielectric material parameter from high-K to low-K in the spacer regions, allowing for reduced spacing between gate and source/drain while maintaining low parasitic capacitance. This parameter change enables area reduction without the harmful side effect of increased parasitic capacitance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration results in faster transistor switching and improved signal propagation characteristics by minimizing parasitic capacitance between source/drain contacts and cap metal, enhancing overall performance in integrated circuits.
Implementation Method 1
The second dielectric spacer layer is a low-K dielectric layer
Data Source
AI summary
An integrated circuit includes a nanosheet transistor having a plurality of stacked channels, a gate electrode surrounding the stacked channels, a source/drain region, and a source/drain contact. The integrated circuit includes a first dielectric layer between the gate metal and the source/drain contact, a second dielectric layer on the first dielectric layer, and a cap metal on the first gate metal and on a hybrid fin structure. The second dielectric layer is on the hybrid fin structure between the cap metal and the source/drain contact.