Self-Aligned Nano Sheet Spacer Fabrication
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Solution Overview
Problem
Current methods for fabricating nano sheet transistors involve complex silicon sheet recess and divot fill processes without adequate control over spacer uniformity, making it desirable to develop a simplified process for forming uniform nano sheet spacers.
Innovation Solution
A method involving the formation of intermediate semiconductor devices with a substrate, multiple layers, and a gate structure, where an oxide layer is deposited and etched to form replacement sidewall spacers, followed by etching to create stack structures with recesses, and finally, low k material is deposited and etched to form self-aligned sidewall spacers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional silicon sheet recess and divot fill processes are used, then nano sheet transistor structures can be formed, but the process complexity increases and spacer uniformity cannot be adequately controlled
Solution Approach 1:
The patent applies preliminary action by forming replacement sidewall spacers before creating the stack structures. These replacement spacers are deposited and etched in advance to define the precise locations where stack structures will later be formed, ensuring uniform spacing is established before the actual nano sheet stacking occurs. This preliminary positioning action enables controlled spacer formation without requiring complex subsequent adjustments.
Solution Approach 2:
The patent introduces replacement sidewall spacers as intermediary structures that temporarily serve as placeholders and alignment references. These intermediary spacers are formed using oxide material, which can be selectively removed later, allowing them to mediate the positioning process without interfering with the final device structure. The replacement spacers act as a bridge between the gate structure and the eventual nano sheet stack positioning.
2Productivity
If simplified processes are used to reduce fabrication steps, then productivity increases, but achieving uniform spacer formation becomes more difficult
Solution Approach 1:
The patent employs self-service through self-aligned formation processes where the replacement sidewall spacers automatically define the positioning for subsequent stack structure formation. The etching steps are designed to self-align to the replacement spacers, eliminating the need for separate alignment procedures. This self-aligning mechanism maintains precision while reducing the number of lithography and alignment steps required, thereby improving productivity without sacrificing spacer uniformity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the process for achieving uniform nano sheet spacers, enhancing the fabrication of nano sheet transistors with improved uniformity and efficiency.
Implementation Method 1
depositing an oxide layer over the device
Implementation Method 2
etching the oxide layer to form replacement sidewall spacers
Implementation Method 3
etching the multiple layers to form at least one stack structure
Data Source
AI summary
Devices and methods of fabricating integrated circuit devices for forming uniform nano sheet spacers self-aligned to the channel are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate, multiple layers disposed on the substrate, and at least one gate structure disposed on the multiple layers; depositing an oxide layer over the device; etching the oxide layer to form replacement sidewall spacers positioned on left and right sides of the at least one gate structure; etching the multiple layers to form at least one stack structure; and forming a plurality of recesses within the at least one stack structure. Also disclosed is an intermediate semiconductor, which includes, for instance: a substrate; and at least one stack structure disposed on the substrate, the at least one stack structure having an upper portion and a base portion, wherein a plurality of recesses are located within the base portion.