Nanosheet SRAM Width Tapering for Read-Write Margin Balance
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Solution Overview
Problem
Existing nanosheet transistor-based SRAM devices face challenges in achieving the optimal current strengths for pull-down, pass-gate, and pull-up transistors, which is crucial for enhancing reading and writing margins.
Innovation Solution
The SRAM device is designed with transistors based on nanosheets of varying widths, where the pull-down transistors have the widest nanosheets, the pass-gate transistors have intermediate-width nanosheets, and the pull-up transistors have the narrowest nanosheets, ensuring optimal current distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If different number of fins are used for each transistor type in fin-FET based SRAM, then optimal current strengths are achieved, but this solution cannot be applied to nanosheet transistor based SRAM
Solution Approach 1:
The patent applies local quality by varying the width of nanosheets for different transistor types (PD, PG, PU) within the SRAM cell. Each transistor type receives nanosheets with specifically optimized widths to achieve the desired current strength characteristics, analogous to using different fin counts in fin-FET SRAM but adapted to nanosheet architecture.
2Ease of manufacture
If nanosheets of uniform width are used for all transistors, then manufacturing is simplified, but optimal current distribution for reading and writing margins cannot be achieved
Solution Approach 1:
The patent implements local quality by specifying different nanosheet widths for different transistor types. The PD transistors use wider nanosheets (first width) for stronger current, PG transistors use intermediate width nanosheets (second width), and PU transistors use narrowest nanosheets (third width), optimizing current distribution while maintaining manufacturability through a systematic width variation approach.
3Reliability
If pull-down transistors have strongest current, pull-up transistors have weakest current, and pass-gate transistors have medium current, then reading and writing margins are enhanced, but this requires complex transistor configuration
Solution Approach 1:
The patent achieves the desired current distribution (PD strongest, PU weakest, PG medium) through local quality variation in nanosheet widths rather than complex interconnections. The configuration is simplified by aligning one side of nanosheet sets and using systematic width progression (first width > second width > third width), reducing design complexity while maintaining performance.
Data Source
AI summary
Embodiments of present invention provide a static random-access-memory (SRAM). The SRAM includes a first and a second pull-down (PD) transistor having respectively a first and a fourth set of nanosheets of a first width; a first and a second pass-gate (PG) transistor having respectively a second and a fifth set of nanosheets of a second width; and a first and a second pull-up (PU) transistor having respectively a third and a sixth set of nanosheets of a third width, wherein the first width is wider than the second width, the second width is wider than the third width, the first set of nanosheets is substantially aligned with the second set of nanosheets at one side of the first and second sets of nanosheets, and the fourth set of nanosheets is substantially aligned with the fifth set of nanosheets at one side of the fourth and fifth sets of nanosheets.