Nanosheet SRAM Sidewall Image Transfer Width Tuning
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Solution Overview
Problem
Conventional sidewall image transfer (SIT) processes for forming nanosheet SRAM result in uniform nanosheet widths and spacings for all transistors, leading to reduced SRAM density due to the quantization effect, which necessitates the removal of dummy nanosheets to meet ground rule requirements.
Innovation Solution
A method is developed to independently tune the widths of n-type and p-type field effect transistor nanosheets using a sidewall image transfer process, allowing for different spacings between them by forming multiple nanosheet stacks with varying widths and spacings using a single spacer material, enabling the formation of wider nFET and narrower pFET structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional SIT process is used to form nanosheet SRAM, then the process is simple and uniform, but the nanosheet width and spacing are the same for all transistors resulting in reduced SRAM density
Solution Approach 1:
The patent segments the nanosheet formation process by creating different nanosheet stacks (first stack for nFET, second stack for pFET) with different widths and spacings. This is achieved through selective etching of sacrificial nanosheet stacks and forming separate mandrels for each transistor type, allowing independent optimization of nFET and pFET dimensions to improve SRAM density while maintaining manufacturing feasibility
Solution Approach 2:
The patent applies local quality by giving different nanosheet widths to different transistor types: wider nanosheets for nFET and narrower nanosheets for pFET. This localized differentiation allows each transistor type to have optimal dimensions for its specific electrical requirements, thereby improving overall SRAM density without requiring uniform dimensions across all transistors
2Manufacturing precision
If dummy nanosheet is removed to enlarge spacing between nFET and pFET, then ground rule requirements are met, but N-P spacing becomes larger than needed reducing SRAM density
Solution Approach 1:
The patent applies preliminary action by pre-forming mandrels at different locations and heights before nanosheet deposition. The first mandrel is formed at a first location and the second mandrel at a second location, allowing precise control of nanosheet spacing from the outset. This eliminates the need for dummy nanosheets and subsequent removal, as the correct spacing is established during the formation process itself
Solution Approach 2:
The patent changes the spacing parameter by forming nanosheet stacks with different spacings based on transistor type. The first nanosheet stack (nFET) has a first spacing and the second nanosheet stack (pFET) has a second spacing, allowing optimization of N-P spacing to meet ground rules without excessive spacing that would reduce density
3Ease of manufacture
If same nanosheet width is used for all transistors, then the SIT process is straightforward, but optimal SRAM performance requiring different widths for nFET and pFET cannot be achieved
Solution Approach 1:
The patent applies local quality by giving different nanosheet widths to different transistor types: wider nanosheets for nFET and narrower nanosheets for pFET. This localized differentiation allows each transistor type to have optimal dimensions for its specific electrical requirements, thereby improving SRAM performance while using a modified but still practical SIT process
Solution Approach 2:
The patent segments the nanosheet formation into separate processes for nFET and pFET. First nanosheet stacks are formed with wider widths for nFET, then second nanosheet stacks are formed with narrower widths for pFET. This segmentation allows optimization of each transistor type's performance characteristics while maintaining a systematic manufacturing approach
Data Source
AI summary
A method is presented for constructing high-density static random access memory (SRAM). The method includes forming a nanosheet SRAM by a sidewall image transfer (SIT) process and independently tuning widths of n-type field effect transistor (nFET) nanosheet structures and p-type field effect transistor (pFET) nanosheet structures of the nanosheet SRAM. The nFET nanosheet structures have a first width and the pFET nanosheet structures have a second width, the first width being greater than the second width. A distance between an nFET nanosheet structure and an adjacent pFET nanosheet structure is greater than a distance between two adjacent pFET nanosheet structures.