Nanosheet Semiconductor Stack Layout for Uniform Threshold Voltage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor structures with nanosheet transistors face challenges in achieving uniform threshold voltages due to difficulties in filling empty spaces within multilayered fins with gate electrode materials, leading to non-uniform gate electrode thicknesses and varying electrical performance.
Innovation Solution
The solution involves altering the spaces between adjacent channel layers in each semiconductor stack and modifying the compositions of the channel layers, specifically increasing the germanium content in the lowermost channel layer, to ensure uniform threshold voltages across nanosheet transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multilayered fins are made relatively tall to accommodate multiple channel layers, then the number of nanosheet transistors per fin increases, but it becomes difficult to fill the empty space in the deeper position of the fins with gate electrode materials uniformly
Solution Approach 1:
The patent applies preliminary action by forming a mandrel structure before depositing the gate electrode material. The mandrel is positioned to extend from the top surface to the bottom surface of the multilayered fin, providing a template that guides the conformal deposition process. This preliminary structure ensures that gate electrode material is deposited uniformly throughout the entire depth of the tall fin, solving the filling difficulty without compromising the high transistor density.
Solution Approach 2:
The mandrel acts as an intermediary structure that facilitates the uniform deposition of gate electrode material in tall multilayered fins. By providing a physical template and deposition surface that extends to the bottom of the fin, the mandrel mediates between the deposition process and the deep fin structure, enabling uniform material distribution that would otherwise be difficult to achieve directly.
2Reliability
If gate electrode layers are deposited to fill empty spaces in deep fin positions, then complete coverage is achieved, but the thicknesses of gate electrode layers between nanosheet transistors become non-uniform
Solution Approach 1:
The mandrel is formed in advance as a preliminary structure that defines the deposition geometry. During conformal deposition, the gate electrode material coats the mandrel surface uniformly from top to bottom, ensuring both complete coverage and uniform thickness. The mandrel's pre-positioned geometry controls the deposition process to achieve consistent thickness throughout the deep fin structure.
Solution Approach 2:
The patent changes the deposition parameters by using conformal deposition methodology where the mandrel's presence alters the deposition field distribution. This parameter change ensures that the deposition process maintains uniform thickness control even in deep fin regions, achieving both complete coverage and thickness uniformity that would be difficult to obtain with conventional deposition methods.
Data Source
Figure 1
Figure 2A~2B
Figure 3A~3B
AI summary
A semiconductor structure includes several semiconductor stacks over a substrate, and each of the semiconductor stacks extends in a first direction, wherein adjacent semiconductor stacks are spaced apart from each other in a second direction, which is different from the first direction. Each of the semiconductor stacks includes channel layers above the substrate and a gate structure across the channel layers. The channel layers are spaced apart from each other in the third direction. The gate structure includes gate dielectric layers around the respective channel layers, and a gate electrode along sidewalls of the gate dielectric layers and a top surface of the uppermost gate dielectric layer. The space in the third direction between the two lowermost channel layers is greater than the space in the third direction between the two uppermost channel layers in the same semiconductor stack.