Nanosheet Transistor Stack Spacing for Multiple Threshold Voltages
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Solution Overview
Problem
Existing nanosheet FET devices lack the capability to achieve multiple threshold voltages in a stacked configuration, which is essential for advanced integrated circuit applications.
Innovation Solution
A method is developed to form a vertical stack of transistors with different threshold voltages by using first and second nanosheets with distinct spacings and dipole gate dielectric materials, along with a workfunction metal stack that pinches off in specific spacings to achieve multiple threshold voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If etch back processes are used to form different threshold voltages, then multiple threshold voltages can be achieved, but transistor damage occurs and integration is complicated
Solution Approach 1:
The patent applies local quality by creating different spacing configurations in specific regions of the nanosheet stack. First and second spacings are defined between adjacent nanosheets, with the first spacing being greater than the second spacing in certain regions. This local variation in spacing allows different threshold voltages to be achieved in different regions without requiring etch back processes, thereby preventing transistor damage while maintaining the ability to create multiple threshold voltages.
2Adaptability or versatility
If etch back processes are used to form different threshold voltages, then multiple threshold voltages can be achieved, but integration complexity increases
Solution Approach 1:
The patent employs parameter changes by varying the spacing between nanosheets (first spacing versus second spacing) to achieve different threshold voltages. By controlling the geometric parameters of the nanosheet configuration rather than using etch back processes, the method simplifies the integration process. The different spacings create different effective gate control regions, enabling multiple threshold voltages through a single formation process without additional etch back steps.
3Adaptability or versatility
If different nanosheet spacings are used, then multiple threshold voltages are achieved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies preliminary action by pre-configuring the nanosheet stack with different spacings during the formation process. The first and second spacings are established in advance through the nanosheet stacking process itself, before any threshold voltage differentiation is needed. This preliminary configuration of different spacings allows subsequent processing steps to proceed without requiring precise etch back operations, thereby reducing manufacturing precision requirements while still achieving multiple threshold voltages.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies integration, reduces gate height, and improves yield by allowing for the formation of complementary devices with different threshold voltages without requiring etch back of workfunction metals, thereby enabling more efficient semiconductor structure fabrication.
Implementation Method 1
first dipole gate dielectric material being formed around the first nanosheets, second dipole gate dielectric material being formed around the second nanosheets
Data Source
AI summary
Embodiments of the invention include forming a first transistor having first nanosheets, first dipole gate dielectric material being formed around the first nanosheets. An aspect includes forming a second transistor comprising second nanosheets, second dipole gate dielectric material being formed around the second nanosheets, the first and second transistors being in a vertical stack, a first spacing between the first nanosheets being different from a second spacing between the second nanosheets. An aspect includes forming a workfunction metal stack having a first workfunction metal and a second workfunction metal, the first and second workfunction metals being formed between the first nanosheets, the first workfunction metal being formed to pinch off in the second spacing between the second nanosheets such that the second workfunction metal is absent in the second spacing between the second nanosheets.